buzzword
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| * Non minimal adaptive routing can have livelocks | * Non minimal adaptive routing can have livelocks | ||
| + | ===== Lecture 32 (4/30 Wed.) ===== | ||
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| + | * Serialized code section | ||
| + | * Degrade performance | ||
| + | * Waste energy | ||
| + | * Heterogeneous cores | ||
| + | * Can execute serialized portion on a powerful large core | ||
| + | * Tradeoff between multiple small cores, multiple large cores or heterogenerous cores | ||
| + | * Critical section | ||
| + | * bottleneck in several multithreaded workloads | ||
| + | * Assymmetry can help | ||
| + | * Accelerated critical section | ||
| + | * Use a large core to run serialized portion of the code | ||
| + | * How to correctly support ACS | ||
| + | * False serialization | ||
| + | * Handling private/shared data | ||
| + | * BIS | ||
| + | * Ideltify the bottleneck | ||
| + | * Serial bottleneck | ||
| + | * Barrier | ||
| + | * Critical section | ||
| + | * Pipeline stages | ||
| + | * Application might wait on different types of bottlenecks | ||
| + | * Allow bottleneckcall and bottleneckreturn | ||
| + | * Acceleration can be done in multiple ways | ||
| + | * ship to a big core | ||
| + | * increase the frequency | ||
| + | * Priorize the thread in share resources (memory scheduler always schedule reqeusts from the thread first, etc.) | ||
| + | * Bottleneck table keeps track of different thread's bottleneck and determine the criticality | ||
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| + | ===== Lecture 33 (5/2 Fri.) ===== | ||
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| + | * DRAM scaling problem | ||
| + | * Possible solutions to the scaling problem | ||
| + | * Less leakage DRAM | ||
| + | * Heterogeneous DRAM (TL-DRAM, etc.) | ||
| + | * Add more functionality to DRAM | ||
| + | * Denser design (3D stack) | ||
| + | * Different technology | ||
| + | * NVM | ||
| + | * Non volatile memory | ||
| + | * Resistive memory | ||
| + | * PCM | ||
| + | * Inject current to change the phase | ||
| + | * Scales better than DRAM | ||
| + | * Multiple bits per cell | ||
| + | * Wider resistence range | ||
| + | * No refresh is needed | ||
| + | * Downside: Latency and write endurance | ||
| + | * STT-MRAM | ||
| + | * Inject current to change the polarity | ||
| + | * Memristor | ||
| + | * Inject current to change the structure | ||
| + | * Persistency - data stay there even without power | ||
| + | * Unified memory and storage management (persistent data structure) - Single level store | ||
| + | * Improve energy and performance | ||
| + | * Simplify programming model | ||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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