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* Multi cycle design | * Multi cycle design | ||
+ | ===== Lecture 6 (1/27 Mon.) ===== | ||
+ | |||
+ | * Microcoded/Microprogrammed machines | ||
+ | * States | ||
+ | * Microinstructions | ||
+ | * Microsequencing | ||
+ | * Control store - Product control signals | ||
+ | * Microsequencer | ||
+ | * Control signal | ||
+ | * What do they have to control? | ||
+ | * Instruction processing cycle | ||
+ | * Latch signals | ||
+ | * State machine | ||
+ | * State variables | ||
+ | * Condition code | ||
+ | * Steering bits | ||
+ | * Branch enable logic | ||
+ | * Difference between gating and loading? (write enable vs. driving the bus) | ||
+ | * Memory mapped I/O | ||
+ | * Hardwired logic | ||
+ | * What control signals come from hardwired logic? | ||
+ | * Variable latency memory | ||
+ | * Handling interrupts | ||
+ | * Difference betwen interrupts and exceptions | ||
+ | * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | ||
+ | * Updating machine behavior | ||
+ | * Horizontal microcode | ||
+ | * Vertical microcode | ||
+ | * Primitives | ||
+ | |||
+ | ===== Lecture 7 (1/29 Wed.) ===== | ||
+ | |||
+ | * Pipelining | ||
+ | * Limitations of the multi-programmed design | ||
+ | * Idle resources | ||
+ | * Throughput of a pipelined design | ||
+ | * What dictacts the throughput of a pipelined design? | ||
+ | * Latency of the pipelined design | ||
+ | * Dependency | ||
+ | * Overhead of pipelining | ||
+ | * Latch cost? | ||
+ | * Data forwarding/bypassing | ||
+ | * What are the ideal pipeline? | ||
+ | * External fragmentation | ||
+ | * Issues in pipeline designs | ||
+ | * Stalling | ||
+ | * Dependency (Hazard) | ||
+ | * Flow dependence | ||
+ | * Output dependence | ||
+ | * Anti dependence | ||
+ | * How to handle them? | ||
+ | * Resource contention | ||
+ | * Keeping the pipeline full | ||
+ | * Handling exception/interrupts | ||
+ | * Pipeline flush | ||
+ | * Speculation | ||
+ | * Interlocking | ||
+ | * Multipath execution | ||
+ | * Fine grain multithreading | ||
+ | * No-op (Bubbles in the pipeline) | ||
+ | * Valid bits in the instructions | ||
+ | |||
+ | ===== Lecture 8 (1/31 Fri.) ===== | ||
+ | * Branch prediction | ||
+ | * Different types of data dependence | ||
+ | * Pipeline stalls | ||
+ | * bubbles | ||
+ | * How to handle stalls | ||
+ | * Stall conditions | ||
+ | * Stall signals | ||
+ | * Dependences | ||
+ | * Distant between dependences | ||
+ | * Data forwarding/bypassing | ||
+ | * Maintaining the correct dataflow | ||
+ | * Different ways to design data forwarding path/logic | ||
+ | * Different techniques to handle interlockings | ||
+ | * SW based | ||
+ | * HW based | ||
+ | * Profiling | ||
+ | * Static profiling | ||
+ | * Helps from the software (compiler) | ||
+ | * Superblock optimization | ||
+ | * Analyzing basic blocks | ||
+ | * How to deal with branches? | ||
+ | * Branch prediction | ||
+ | * Delayed branching (branch delay slot) | ||
+ | * Forward control flow/backward control flow | ||
+ | * Branch prediction accuracy | ||
+ | * Profile guided code positioning | ||
+ | * Based on the profile info. position the code based on it | ||
+ | * Try to make the next sequential instruction be the next inst. to be executed | ||
+ | * Trace cache | ||
+ | * Predicate combining (combine predicate for a branch instruction) | ||
+ | * Predicated execution (control dependence becomes data dependence) | ||
+ | * Definition of basic blocks | ||
+ | * Control flow graph |