buzzword
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buzzword [2014/01/22 19:23] rachata |
buzzword [2014/01/29 19:14] rachata |
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| * CPI/IPC | * CPI/IPC | ||
| * CPI of a single cycle microarchitecture | * CPI of a single cycle microarchitecture | ||
| + | |||
| + | ===== Lecture 5 (1/24 Fri.) ===== | ||
| + | |||
| + | * Instruction processing | ||
| + | * Fetch | ||
| + | * Decode | ||
| + | * Execute | ||
| + | * Memory fetch | ||
| + | * Writeback | ||
| + | * Datapath & Control logic in microprocessors | ||
| + | * Different types of instructions (I-type, R-type, etc.) | ||
| + | * Control flow instructions | ||
| + | * Non-control flow instructions | ||
| + | * Delayed slot/Delayed branch | ||
| + | * Single cycle control logic | ||
| + | * Lockstep | ||
| + | * Critical path analysis | ||
| + | * Critical path of a single cycle processor | ||
| + | * Combinational logic & Sequential logic | ||
| + | * Control store | ||
| + | * Tradeoffs of a single cycle uarch | ||
| + | * Dynamic power/Static power | ||
| + | * Speedup calculation | ||
| + | * Parallelism | ||
| + | * Serial bottleneck | ||
| + | * Amdahl's bottleneck | ||
| + | * Design principles | ||
| + | * Common case design | ||
| + | * Critical path design | ||
| + | * Balanced designs | ||
| + | * Multi cycle design | ||
| + | |||
| + | ===== Lecture 6 (1/27 Mon.) ===== | ||
| + | |||
| + | * Microcoded/Microprogrammed machines | ||
| + | * States | ||
| + | * Microinstructions | ||
| + | * Microsequencing | ||
| + | * Control store - Product control signals | ||
| + | * Microsequencer | ||
| + | * Control signal | ||
| + | * What do they have to control? | ||
| + | * Instruction processing cycle | ||
| + | * Latch signals | ||
| + | * State machine | ||
| + | * State variables | ||
| + | * Condition code | ||
| + | * Steering bits | ||
| + | * Branch enable logic | ||
| + | * Difference between gating and loading? (write enable vs. driving the bus) | ||
| + | * Memory mapped I/O | ||
| + | * Hardwired logic | ||
| + | * What control signals come from hardwired logic? | ||
| + | * Variable latency memory | ||
| + | * Handling interrupts | ||
| + | * Difference betwen interrupts and exceptions | ||
| + | * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | ||
| + | * Updating machine behavior | ||
| + | * Horizontal microcode | ||
| + | * Vertical microcode | ||
| + | * Primitives | ||
| + | |||
| + | ===== Lecture 7 (1/29 Wed.) ===== | ||
| + | * Pipelining | ||
| + | * Limitations of the multi-programmed design | ||
| + | * Idle resources | ||
| + | * Throughput of a pipelined design | ||
| + | * What dictacts the throughput of a pipelined design? | ||
| + | * Latency of the pipelined design | ||
| + | * Dependency | ||
| + | * Overhead of pipelining | ||
| + | * Latch cost? | ||
| + | * Data forwarding/bypassing | ||
| + | * What are the ideal pipeline? | ||
| + | * External fragmentation | ||
| + | * Issues in pipeline designs | ||
| + | * Stalling | ||
| + | * Dependency (Hazard) | ||
| + | * Flow dependence | ||
| + | * Output dependence | ||
| + | * Anti dependence | ||
| + | * How to handle them? | ||
| + | * Resource contention | ||
| + | * Keeping the pipeline full | ||
| + | * Handling exception/interrupts | ||
| + | * Pipeline flush | ||
| + | * Speculation | ||
| + | * Interlocking | ||
| + | * Multipath execution | ||
| + | * Fine grain multithreading | ||
| + | * No-op (Bubbles in the pipeline) | ||
| + | * Valid bits in the instructions | ||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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