buzzword
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buzzword [2014/01/17 19:20] rachata |
buzzword [2014/01/27 19:20] rachata |
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| * Performance | * Performance | ||
| * Optimization opportunity | * Optimization opportunity | ||
| + | |||
| + | ===== Lecture 4 (1/22 Wed.) ===== | ||
| + | |||
| + | * Semantic gap | ||
| + | * Small vs. Large semantic gap (CISC vs. RISC) | ||
| + | * Benefit of RISC vs. CISC | ||
| + | * Micro operations/microcode | ||
| + | * Translate complex instructions into smaller instructions | ||
| + | * Parallelism (motivation for RISC) | ||
| + | * Compiler optimization | ||
| + | * Code optimization through translation | ||
| + | * VLIW | ||
| + | * Fixed vs. variable length instructions | ||
| + | * Tradeoffs | ||
| + | * Alignment issues? (fetch/decode) | ||
| + | * Decoding issues? | ||
| + | * Code size? | ||
| + | * Adding additional instructions? | ||
| + | * Memory bandwidth and cache utilization? | ||
| + | * Energy? | ||
| + | * Encoding in variable length instructions | ||
| + | * Structure of Alpha instructions and other uniform decode instructions | ||
| + | * Different type of instructions | ||
| + | * Benefit of knowing what type of instructions | ||
| + | * Speculatively operate future instructions | ||
| + | * x86 and other non-uniform decode instructions | ||
| + | * Tradeoff vs. uniform decode | ||
| + | * Tradeoffs for different number of registers | ||
| + | * Spilling into memory if the number of registers is small | ||
| + | * Compiler optimization on how to manage which value to keep/spill | ||
| + | * Addressing modes | ||
| + | * Benefits? | ||
| + | * Types? | ||
| + | * Different uses of addressing modes? | ||
| + | * Various ISA-level tradeoffs | ||
| + | * Virtual memory | ||
| + | * Unalign memory access/aligned memory access | ||
| + | * Cost vs. benefit of unaligned access | ||
| + | * ISA specification | ||
| + | * Things you have to obey/specifie in the ISA specification | ||
| + | * Architectural states | ||
| + | * Microarchitecture implements how arch. state A transformed to the next arch. state A' | ||
| + | * Single cycle machines | ||
| + | * Critical path in the single cycle machine | ||
| + | * Multi cycle machines | ||
| + | * Functional units | ||
| + | * Performance metrics | ||
| + | * CPI/IPC | ||
| + | * CPI of a single cycle microarchitecture | ||
| + | |||
| + | ===== Lecture 5 (1/24 Fri.) ===== | ||
| + | |||
| + | * Instruction processing | ||
| + | * Fetch | ||
| + | * Decode | ||
| + | * Execute | ||
| + | * Memory fetch | ||
| + | * Writeback | ||
| + | * Datapath & Control logic in microprocessors | ||
| + | * Different types of instructions (I-type, R-type, etc.) | ||
| + | * Control flow instructions | ||
| + | * Non-control flow instructions | ||
| + | * Delayed slot/Delayed branch | ||
| + | * Single cycle control logic | ||
| + | * Lockstep | ||
| + | * Critical path analysis | ||
| + | * Critical path of a single cycle processor | ||
| + | * Combinational logic & Sequential logic | ||
| + | * Control store | ||
| + | * Tradeoffs of a single cycle uarch | ||
| + | * Dynamic power/Static power | ||
| + | * Speedup calculation | ||
| + | * Parallelism | ||
| + | * Serial bottleneck | ||
| + | * Amdahl's bottleneck | ||
| + | * Design principles | ||
| + | * Common case design | ||
| + | * Critical path design | ||
| + | * Balanced designs | ||
| + | * Multi cycle design | ||
| + | |||
| + | ===== Lecture 6 (1/27 Mon.) ===== | ||
| + | |||
| + | * Microcoded/Microprogrammed machines | ||
| + | * States | ||
| + | * Microinstructions | ||
| + | * Microsequencing | ||
| + | * Control store - Product control signals | ||
| + | * Microsequencer | ||
| + | * Control signal | ||
| + | * What do they have to control? | ||
| + | * Instruction processing cycle | ||
| + | * Latch signals | ||
| + | * State machine | ||
| + | * State variables | ||
| + | * Condition code | ||
| + | * Steering bits | ||
| + | * Branch enable logic | ||
| + | * Difference between gating and loading? (write enable vs. driving the bus) | ||
| + | * Memory mapped I/O | ||
| + | * Hardwired logic | ||
| + | * What control signals come from hardwired logic? | ||
| + | * Variable latency memory | ||
| + | * Handling interrupts | ||
| + | * Difference betwen interrupts and exceptions | ||
| + | * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | ||
| + | * Updating machine behavior | ||
| + | * Horizontal microcode | ||
| + | * Vertical microcode | ||
| + | * Primitives | ||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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