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buzzword [2014/01/17 19:18] rachata |
buzzword [2015/01/16 19:47] kevincha [Lecture 3 (1/17 Fri.)] |
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====== Buzzwords ====== | ====== Buzzwords ====== | ||
- | Buzzwords are terms that are mentioned during lecture which are particularly important to understand thoroughly. This page tracks the buzzwords for each of the lectures and can be used as a reference for finding gaps in your understanding of course material. | + | Buzzwords are terms that are mentioned during lecture which are particularly important to understand thoroughly. This page tracks the buzzwords for each of the lectures and can be used as a reference for finding gaps in your understanding of course material. |
- | + | ||
- | ===== Lecture 1 (1/13 Mon.) ===== | + | |
+ | ===== Lecture 1 (1/12 Mon.) ===== | ||
* Level of transformation | * Level of transformation | ||
* Algorithm | * Algorithm | ||
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* Compiler | * Compiler | ||
* Cross abstraction layers | * Cross abstraction layers | ||
- | * Expose an interface | ||
* Tradeoffs | * Tradeoffs | ||
* Caches | * Caches | ||
- | * Multi-thread | + | * DRAM/memory controller |
- | * Multi-core | + | * DRAM banks |
- | * Unfairness | + | |
- | * DRAM controller/Memory controller | + | |
- | * Memory hog | + | |
* Row buffer hit/miss | * Row buffer hit/miss | ||
* Row buffer locality | * Row buffer locality | ||
- | * Streaming access/ Random access | + | * Unfairness |
- | * DRAM refresh | + | * Memory performance hog |
- | * Retention time | + | * Shared DRAM memory system |
- | * Profiling DRAM retention time | + | * Streaming access vs. random access |
+ | * Memory scheduling policies | ||
+ | * Scheduling priority | ||
+ | * Retention time of DRAM | ||
+ | * Process variation | ||
+ | * Retention time profile | ||
* Power consumption | * Power consumption | ||
- | * Wimpy cores | ||
* Bloom filter | * Bloom filter | ||
- | * Pros/Cons | + | * Hamming code |
- | * False Positive | + | * Hamming distance |
- | * Simulation | + | * DRAM row hammer |
- | * Memory performance attacks | + | |
- | * RTL design | + | |
- | ===== Lecture 2 (1/15 Wed.) ===== | + | ===== Lecture 2 (1/14 Wed.) ===== |
- | + | ||
- | * Optimizing for energy/ Optimizing for the performance | + | |
- | * Generally you should optimize for the users | + | |
- | * state-of-the-art | + | |
- | * RTL Simulation | + | |
- | * Long, slow and can be costly | + | |
- | * High level simulation | + | |
- | * What should be employed? | + | |
- | * Important to get the idea of how they are implemented in RTL | + | |
- | * Allows designer to filter out techniques that do not work well | + | |
- | * Design points | + | |
- | * Design processors to meet the design points | + | |
- | * Software stack | + | |
- | * Design decisions | + | |
- | * Datacenters | + | |
- | * MIPS R2000 | + | |
- | * What are architectural techniques that improve the performance of a processor over MIPS 2000 | + | |
* Moore's Law | * Moore's Law | ||
+ | * Algorithm --> step-by-step procedure to solve a problem | ||
* in-order execution | * in-order execution | ||
* out-of-order execution | * out-of-order execution | ||
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* Scaling issue | * Scaling issue | ||
* Transister are getting smaller | * Transister are getting smaller | ||
+ | * Key components of a computer | ||
+ | * Design points | ||
+ | * Design processors to meet the design points | ||
+ | * Software stack | ||
+ | * Design decisions | ||
+ | * Datacenters | ||
* Reliability problems that cause errors | * Reliability problems that cause errors | ||
* Analogies from Kuhn's "The Structure of Scientific Revolutions" (Recommended book) | * Analogies from Kuhn's "The Structure of Scientific Revolutions" (Recommended book) | ||
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* Computation | * Computation | ||
* Communication | * Communication | ||
- | * Storage | + | * Storage |
- | * DRAM | + | * DRAM |
- | * NVRAM (Non-volatile memory): PCM, STT-MRAM | + | * NVRAM (Non-volatile memory): PCM, STT-MRAM |
- | * Storage (Flash/Harddrive) | + | * Storage (Flash/Harddrive) |
* Von Neumann Model (Control flow model) | * Von Neumann Model (Control flow model) | ||
* Stored program computer | * Stored program computer | ||
- | * Properties of Von Neumann Model: Stored program, sequential instruction processing | + | * Properties of Von Neumann Model: Stored program, sequential instruction processing |
- | * Unified memory | + | * Unified memory |
- | * When does an instruction is being interpreted as an instruction (as oppose to a datum)? | + | * When does an instruction is being interpreted as an instruction (as oppose to a datum)? |
- | * Program counter | + | * Program counter |
- | * Examples: x86, ARM, Alpha, IBM Power series, SPARC, MIPS | + | * Examples: x86, ARM, Alpha, IBM Power series, SPARC, MIPS |
* Data flow model | * Data flow model | ||
* Data flow machine | * Data flow machine | ||
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* Tradeoffs between control-driven and data-driven | * Tradeoffs between control-driven and data-driven | ||
* What are easier to program? | * What are easier to program? | ||
- | * Which are easy to compile? | + | * Which are easy to compile? |
- | * What are more parallel (does that mean it is faster?) | + | * What are more parallel (does that mean it is faster?) |
- | * Which machines are more complex to design? | + | * Which machines are more complex to design? |
* In control flow, when a program is stop, there is a pointer to the current state (precise state). | * In control flow, when a program is stop, there is a pointer to the current state (precise state). | ||
* ISA vs. Microarchitecture | * ISA vs. Microarchitecture | ||
* Semantics in the ISA | * Semantics in the ISA | ||
- | * uArch should obey the ISA | + | * uArch should obey the ISA |
- | * Changing ISA is costly, can affect compatibility. | + | * Changing ISA is costly, can affect compatibility. |
* Instruction pointers | * Instruction pointers | ||
* uArch techniques: common and powerful techniques break Vonn Neumann model if done at the ISA level | * uArch techniques: common and powerful techniques break Vonn Neumann model if done at the ISA level | ||
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* Out-of-order executions | * Out-of-order executions | ||
* etc. | * etc. | ||
- | * Design techniques | + | * Design techniques |
- | * Adder implementation (Bit serial, ripple carry, carry lookahead) | + | * Adder implementation (Bit serial, ripple carry, carry lookahead) |
- | * Connection machine (an example of a machine that use bit serial to tradeoff latency for more parallelism) | + | * Connection machine (an example of a machine that use bit serial to tradeoff latency for more parallelism) |
* Microprocessor: ISA + uArch + circuits | * Microprocessor: ISA + uArch + circuits | ||
* What are a part of the ISA? Instructions, memory, etc. | * What are a part of the ISA? Instructions, memory, etc. | ||
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* Things that are not suppose to be visible to the programmer/software but typically make the processor faster and/or consumes less power and/or less complex | * Things that are not suppose to be visible to the programmer/software but typically make the processor faster and/or consumes less power and/or less complex | ||
- | ===== Lecture 3 (1/17 Wed.) ===== | + | ===== Lecture 3 (1/17 Fri.) ===== |
- | * Design tradeoffs | + | * Microarchitecture |
- | * Macro Architectures | + | * Three major tradeoffs of computer architecture |
- | * Reconfiguribility vs. specialized designs | + | * Macro-architecture |
- | * Parallelism (instructions, data parallel) | + | * LC-3b ISA |
- | * Uniform decode (Example: Alpha) | + | * Unused instructions |
- | * Steering bits (Sub-opcode) | + | * Bit steering |
- | * 0,1,2,3 address machines | + | * Instruction processing style |
- | * Stack machine | + | * 0,1,2,3 address machines |
- | * Accumulator machine | + | * Stack machine |
- | * 2-operand machine | + | * Accumulator machine |
- | * 3-operand machine | + | * 2-operand machine |
- | * Tradeoffs between 0,1,2,3 address machines | + | * 3-operand machine |
- | * Instructions/Opcode/Operade specifiers (i.e. addressing modes) | + | * Tradeoffs between 0,1,2,3 address machines |
- | * Simply vs. complex data type (and their tradeoffs) | + | * Postfix notation |
- | * Semantic gap | + | * Instructions/Opcode/Operade specifiers (i.e. addressing modes) |
- | * Translation layer | + | * Simply vs. complex data type (and their tradeoffs) |
- | * Addressability | + | * Semantic gap and level |
- | * Byte/bit addressable machines | + | * Translation layer |
- | * Virtual memory | + | * Addressability |
- | * Big/little endian | + | * Byte/bit addressable machines |
- | * Benefits of having registers (data locality) | + | * Virtual memory |
- | * Programmer visible (Architectural) state | + | * Big/little endian |
- | * Programmers can access this directly | + | * Benefits of having registers (data locality) |
- | * What are the benefits? | + | * Programmer visible (Architectural) state |
- | * Microarchitectural state | + | * Programmers can access this directly |
- | * Programmers cannot access this directly | + | * What are the benefits? |
- | * Evolution of registers (from accumulators to registers) | + | * Microarchitectural state |
- | * Different types of instructions | + | * Programmers cannot access this directly |
- | * Control instructions | + | * Evolution of registers (from accumulators to registers) |
- | * Data instructions | + | * Different types of instructions |
- | * Operation instructions | + | * Control instructions |
- | * Addressing modes | + | * Data instructions |
- | * Tradeoffs (complexity, flexibility, etc.) | + | * Operation instructions |
- | * Orthogonal ISA | + | * Addressing modes |
- | * Addressing modes that are orthogonal to instructino types | + | * Tradeoffs (complexity, flexibility, etc.) |
- | * Vectors vs. non vectored interrupts | + | * Orthogonal ISA |
- | * Complex vs. simple instructions | + | * Addressing modes that are orthogonal to instruction types |
- | * Tradeoffs | + | * I/O devices |
- | * RISC vs. CISC | + | * Vectored vs. non-vectored interrupts |
- | * Tradeoff | + | * Complex vs. simple instructions |
- | * Backward compatibility | + | * Tradeoffs |
- | * Performance | + | * RISC vs. CISC |
- | * Optimization opportunity | + | * Tradeoff |
+ | * Backward compatibility | ||
+ | * Performance | ||
+ | * Optimization opportunity | ||
+ | * Translation | ||