Due November 11, 1998
Draft until November 4
Problem 1:
Awaiting a problem from Erik...
Problem 2. Vector Architecture
A particular vector computer design has the characteristics & assumptions given below. Some of the assumptions such as ignoring bank conflicts are made to make the problem easier and are obviously not realistic.
Latency | Clock ticks of latency |
Vector instruction dispatch | 1 |
VAG setup | 1 |
Address reaches memory bank | 3 |
DRAM read latency (ignore time to complete cycle) | 4 |
Data returns from memory bank after access via bus | 3 |
VDS delay | 1 |
Adder delay (starting when both operands available) | 4 |
VDS delay | 1 |
Result sent to memory bank via bus (address & data) | 3 |
Data written in to DRAM (ignore time to complete cycle) | 4 |
A 4-element vector addition takes 4 clock cycles to issue ("vload", "vload", "vadd", "vstore"). What is the elapsed time for a 4-element vector addition in clock ticks? Provide a spreadsheet printout or other table diagram illustrating how you got this solution (similar to the spreadsheets in lecture 16, but using columns and latencies appropriate to the table above).
18-548/15-548 home page.