The main design change made was covered in Jose’s status report, which is the asynchronous FIFO (rather than a normal FIFO) for managing data between the general FPGA and audio CODEC system. This was done after a talk with teammates where we realized that there was a need for clock domain crossing in our system. While necessary for our system to function and send out data properly, it does not incur any external costs aside from the time spend implementing\/debugging (which has only been around three hours so far). Overall, though, our schedule has not changed and we look to keep progressing with our project as planned (and begin doing more thorough integration with our FPGA before the interim demo). Our biggest risk so far is simply getting audio output integration with signals working, since it serves as the backbone for our system. Hopefully, it’s up and running by the following week. In the case that progress staggers, we plan on spending more time than allotted to the course next week to get it working (in addition to the time spent on the other portions of the system.<\/p>\n","protected":false},"excerpt":{"rendered":"
The main design change made was covered in Jose’s status report, which is the asynchronous FIFO (rather than a normal FIFO) for managing data between the general FPGA and audio CODEC system. This was done after a talk with teammates where we realized that there was a need for clock domain crossing in our system. … <\/p>\n