![\"\"](\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s26-teamd0\/wp-content\/uploads\/sites\/423\/2026\/03\/Param_Reg-300x262.png\")
<\/p>\nThis week, I worked on the design report, writing the subsections under system implementation,\u00a0 the test and validation section,\u00a0 and the section on ethical and societal considerations. This helped me better think through the design for the various modules, and start drafting up block diagrams for them. Additionally, I wrote the RTL for the delay module in the system. I designed an additional param_register submodule to store the parameters, allowing for basic manipulation of the stored value, according to the following block diagram:<\/p>\n
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From here, the block diagram for the delay component was:<\/p>\n
![\"\"](\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s26-teamd0\/wp-content\/uploads\/sites\/423\/2026\/03\/delay-300x209.png\")
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The multiplication operation was implemented using an on-chip DSP slice, since I assumed that any custom implementation would take far longer to create a circuit around the same speed. The DE10-Standard FPGA also contains double-ported BRAM, meaning that the concurrent read\/write operation necessary for this component can be natively supported. Next week, I hope to implement the RTL for the IIR and FIR components.<\/p>\n
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<\/p>\n","protected":false},"excerpt":{"rendered":"
This week, I worked on the design report, writing the subsections under system implementation,\u00a0 the test and validation section,\u00a0 and the section on ethical and societal considerations. This helped me better think through the design for the various modules, and start drafting up block diagrams for them. Additionally, I wrote the RTL for the delay … <\/p>\n