This week we focussed on wrapping up the auxiliary tasks that lead up to the final stage of the project where we’ll focus on iterating on the hardware accelerator. Namely:
- Setting up our benchmarking and profiling system for the baseline.
- Setting up the FPGA connectivity and synthesis flow.
- Evaluating a Chain of thought alternative model for improving model accuracy.
We managed to complete the benchmarking and profiling system, and eventually decided against using deepseek-r1’s smaller variant, however the FPGA system did not end up working as we expected.
We found that the the FPGA system that we used had some flaws in its WiFi connectivity setup, this leads to us not being able to service multiple clients at the same time.
Our goals for next week are:
- Run our benchmarking and profiling system on a wide spectrum of input tokens, and collect a comprehensive characterization dataset on our Macs.
- Swap to a functional FPGA with WiFi capacity and boot linux as well as our synthesis flow on the board. However, in the duration that the other FPGA takes to arrive, we can still try to synthesize the model onto ours and get that working — but this will only be a viable option if we’re going to use the same FPGA type after changing.
- Preemptively prepare the interconnect from FPGA to laptop and begin drawing a block diagram for the accelerated system.
For status report 2: A was written by Anirudh, B was written by Amelia, and C was written by Andrew.