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Ruslana’s Status Report for 4/12/25

  1. Debugged Tetris and Dr. Mario based on the frames (see Katherine/Bharathi’s status reports for more detail)
  2. Created frame buffer from BRAMs and used it to render vga frame (preinitialized with our tetris.ppm frame). Also upscaled it to support a larger display.
  3. Rendered dmg-acid-test with pure ROM, incorrect but not far off so we proceeded to start debugging entire design on FPGA.
  4. Wrote the APU (4 channels with envelope/sweep/volume/pseudorandom noise manipulation). Unsure if we will get to implement this.
  5. Did some research on the side and came up with a plan to use SDRAM and UART through raspberry pi to support MBC for games that have more memory than FPGA block rams can support (but it seems like we will not have time to do this)
  6. Currently debugging Dr. Mario ROM on fpga + vga setup. Using signal tap and slower clocks to step though the PCs and cross-comparing between simulation and synthesis to check.

Some images throughout the week of the process (signal tap + vga/frame buffer timing bugs):

 

 

 

 

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Bharathi’s Status Report for 4/12/25

Accomplished

DMG PPU (4-color PPU)

Spent a lot of time debugging the many edge cases part of the DMG Acid Test. DMG PPU pretty close to being done and looks almost perfect: 

DMG Acid Test — Fully Integrated Version
DMG Acid Test — Reference Image

CGB PPU (full-color PPU)

No updates here.

APU / CODEC Research

  • Acquired 3.5mm TRS connector for testing on APU.
  • Discussed the APU design / implementation with Ruslana.
  • Researched audio output for APU.

Summary of time spent this week

  • Integration debugging: 20+ hrs
  • APU / Audio research: 2+ hrs
  • DMG Acid Test debugging: 10+ hrs

Schedule / Progress

I believe I’m on schedule and integration going well. We spent a lot of time debugging on simulation and we’ve made great progress fixing a number of different bugs across our design. Our next goal as a group would be get something that is moderately playable by next week.

Next Step(s)

  • More integration debugging (this time on FPGA).
  • Final presentation stuff.
  • APU test on FPGA.

Verification & Validation information is part of our Team Status Report.

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Bharathi’s Status Report for 3/29/25

 

My goal(s) for this week were some subset of:

  • DMG PPU integration (in progress, to be continued).
  • APU test on FPGA (postponed to next week).

Accomplished

DMG PPU (4-color PPU)

PPU integration is in progress. 

 

Integration & debugging in progress
After fixing Scrolling (SCX, SCY) and LCDC related bugs
DMG Acid Test — Reference Image

CGB PPU (full-color PPU)

No updates here.

APU / CODEC Research

Postponed work on APU in favor of getting the PPU integrated and preparing for the demo.

Summary of time spent this week

  • PPU & integration debugging: 12+ hrs

Schedule / Progress

I believe I’m on schedule. Integration is in progress. PPU and MMU are fully integrated, and our test to render a single frame was successful. CPU, MMU, PPU all seem to be talking well but there’s still a lot of integration debugging left.

Next Step(s)

  • More integration debugging.
  • Demo prep.
  • APU test on FPGA.
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Team Status Report for 3/29/25

Progress:

  • Integration
    • MMU and CPU integration has been verified. All tests pass except interrupts (which we are debugging now that the PPU is introduced)
    • Testbench made for full integration
    • Full integration in progress
      • Working on generating a frame of Tetris
      • Working on debugging Acid tests
    • With initialized VRAM/OAM and a few hardcoded PPU registers, we managed to generate a tetris frame. This confirms that the PPU is accessing MMU correctly.

Image

  • I/O
    • New controllers have been assembled

ImageImage

Image
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Ruslana’s Status Report for 3/29/25

Accomplished:

  • Verified MMU and CPU are integrated with all except interrupt tests (which we are now working on, due to also adding the PPU)
  • Integrated all units but APU
  • Made a testbench to test full integration
  • Started debugging all units with Tetris and dmg-acid-test
  • Synthesized all units on Quartus. After catching some latches, we confirmed that it is indeed synthesizable.  We are using the amount of memory that we expect, but surprisingly, there is low LUT usage. Hopefully, this is not an indication that stuff is being optimized away, but the Technology RTL Viewer on Quartus is showing all of the circuitry and fllip-flops for our 3 designs.
  • Image
Next Step:
  • Work on debugging Tetris
Other Notes or Concerns:
  • We are on schedule.
  • The blargg interrupt tests can’t be fully run due to timing optimizations done to the PPU. However, what was able to be run shows that interrupts will probably work.
  • Most MMU bugs have been subtle address calculation problems or actual differing interpretations of spec details that are getting noticed with each test, but no enormous internal failures. It is servicing the PPU and CPU fine.
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Katherine’s Status Report for 3/29/25

Accomplished:

  • Verified MMU and CPU are integrated
  • Integrated all units
  • Made a testbench to test full integration
  • Started debugging all units with Tetris and dmg-acid-test
  • 2 new controllers created
Next Step:
  • Work on debugging Tetris
Other Notes or Concerns:
  • We are on schedule.
  • The blargg interrupt tests can’t be fully run due to timing optimizations done to the PPU. However, what was able to be run shows that interrupts will probably work.
  • Tetris is difficult to debug. To make debugging slightly easier, I am using the software emulator SameBoy to verify our implementation’s functionality.
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Team Status Report for 3/22/25

Progress:

  • Integration
    • MMU and CPU have been integrated
    • Testbench made for MMU and CPU integration
    • MMU and CPU integration debugging is in process.
  • PPU
    • CGB PPU debugging — backgrounds and windows works.
  • MMU
    • BRAM works in testbench
    • IO timer/apu/ppu/interrupt registers work in testbench
    • debugging DMA transfer details but CPU/MMU integration has begun
  • APU
    • Implemented I2S logic — works in simulation.
    • Sketched APU datapath + RTL.
  • I/O
    • New controller has been assembled
Design Changes:
  • Continuing along with clock at 2x CPU frequency for MMU, given that MMU BRAMs have to read out in 2 clock cycles (and we are expecting single cycle delay in CPU case)
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Ruslana’s Status Report for 3/22/25

  • Timer/PPU/APU IO Registers work, in addition to BRAM modules in MMU!
  • Currently (in between typing this report) debugging DMA functionality–MMU is almost completely testbenched enough for integration to be full sent
  • First integration test between CPU/MMU has been written and compiled with a fresh Makefile and a basic tb has been created, and debugging more thoroughly is scheduled for tomorrow
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Bharathi’s Status Report for 3/22/25

 

My goal(s) for this week were some subset of:

  • Validate full WM8731 configuration (postponed to next week).
  • Sketch I2S implementation (completed).
  • DMG PPU integration (postponed to next week).
  • CGB PPU debugging — target: get backgrounds and windows working (completed).

Accomplished

DMG PPU (4-color PPU)

No updates here, I plan to integrate this with the CPU & MMU early next week. 

CGB PPU (full-color PPU)

Backgrounds seem to be mostly functional, but I’m still debugging issues with the sprite palettes.

APU / CODEC Research

Implemented I2S logic — works in simulation.

Sketched datapath for APU + wrote some RTL. Will do a code review for this with Ruslana next week and try a basic test on FPGA.

Summary of time spent this week

  • CGB debugging: 9+ hrs
  • I2S implementation: 2 hrs
  • APU research + datapath + RTL: 4 hrs

Schedule / Progress

I believe I’m on schedule.  I don’t have any new concerns about the PPU or APU largely, but I should really integrate the PPU next week so I can debug some larger tests.

Next Step(s)

  • DMG PPU integration.
  • APU test on FPGA.
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Katherine’s Status Report for 3/22/25

Accomplished:

  • Integrated the CPU and MMU
  • Made a testbench to test the CPU and MMU integration
  • Made another controller.
Next Step:
  • Debugging CPU MMU integration.
  • Integrate PPU.
Other Notes or Concerns:
  • Integration is happening later than expected, but it seems to be going smoothly so far.