Accomplished

• Debugged Tetris and Dr.Mario on VGA with team. Tetris looks mostly functional but the game appears to run 2x faster. Dr.Mario is stuck after the pill is spawned & before it is thrown.
• I spend some time debugging the issue on simulation. Sadly, this was a fairly slow process as many of the bugs in the games we want to play show up somewhat later so I need to run the simulation for a while to get more information but this still offers a lot more visibility so I am optimistic that I will be able to debug the issue with Dr Mario and Tetris.
• Katherine and I also plan to test a few other games on synthesis.

Next Step(s)

• Finish debugging Dr.Mario and Tetris.
• Prep for demo.
• Work on poster, final report.

Accomplished

• Debugged DMG Acid Test — frame rendered appears to be fully correct. Also fixed the missing hand issue on Dr.Mario in simulation.
• Debugged Tetris and Dr.Mario on VGA with team. Tetris looks mostly functional but the game appears to run 2x faster. Dr.Mario is stuck after the pill is spawned & before it is thrown.
• Fixed synthesis issues related to the Audio Test. Technically we have all the pieces for the APU but integrating it is likely to introduce a number of other issues so I have postponed it until we get Dr.Mario and Tetris working perfectly.
• Ruslana and I spent a lot of time investigating the Dr Mario pill issue on simulation. Unfortunately, the bug happens after such a long time that looking at in simulation is not the most productive way to attacking the problem. However, simulation allowed us to get more specific areas / registers / addresses to look at.

Schedule / Progress

We are somewhat behind schedule given the APU status but otherwise integration is going pretty well.

Next Step(s)

• Finish debugging Dr.Mario and Tetris.
• Potentially integrate APU.

Tools/knowledge:

• We need to learn the GameBoy spec thoroughly to implement it correctly. The largest challenge with this was trying to parse the many informal / unofficial documentation (that was usually contradictory).
• I also learnt a lot related to Intel / Altera tooling and designing specifically for FPGAs. Prior to this, most of my hardware experience had been on simulation.
• Implementing the PPU from scratch also forced me to explore more new and complex strategies to testbench my code (both separately and after integration).
• I also got plenty of practice using wave viewers and software debuggers during debugging.

Accomplished

DMG PPU (4-color PPU)

Spent a lot of time debugging the many edge cases part of the DMG Acid Test. DMG PPU pretty close to being done and looks almost perfect: 

CGB PPU (full-color PPU)

No updates here.

APU / CODEC Research

• Acquired 3.5mm TRS connector for testing on APU.
• Discussed the APU design / implementation with Ruslana.
• Researched audio output for APU.

Summary of time spent this week

• Integration debugging: 20+ hrs
• APU / Audio research: 2+ hrs
• DMG Acid Test debugging: 10+ hrs

Schedule / Progress

I believe I’m on schedule and integration going well. We spent a lot of time debugging on simulation and we’ve made great progress fixing a number of different bugs across our design. Our next goal as a group would be get something that is moderately playable by next week.

Next Step(s)

• More integration debugging (this time on FPGA).
• Final presentation stuff.
• APU test on FPGA.

Verification & Validation information is part of our Team Status Report.

 

My goal(s) for this week were some subset of:

• DMG PPU integration (in progress, to be continued).
• APU test on FPGA (postponed to next week).

Accomplished

DMG PPU (4-color PPU)

PPU integration is in progress. 

 

CGB PPU (full-color PPU)

No updates here.

APU / CODEC Research

Postponed work on APU in favor of getting the PPU integrated and preparing for the demo.

Summary of time spent this week

• PPU & integration debugging: 12+ hrs

Schedule / Progress

I believe I’m on schedule. Integration is in progress. PPU and MMU are fully integrated, and our test to render a single frame was successful. CPU, MMU, PPU all seem to be talking well but there’s still a lot of integration debugging left.

Next Step(s)

• More integration debugging.
• Demo prep.
• APU test on FPGA.

 

My goal(s) for this week were some subset of:

• Validate full WM8731 configuration (postponed to next week).
• Sketch I2S implementation (completed).
• DMG PPU integration (postponed to next week).
• CGB PPU debugging — target: get backgrounds and windows working (completed).

Accomplished

DMG PPU (4-color PPU)

No updates here, I plan to integrate this with the CPU & MMU early next week. 

CGB PPU (full-color PPU)

Backgrounds seem to be mostly functional, but I’m still debugging issues with the sprite palettes.

APU / CODEC Research

Implemented I2S logic — works in simulation.

Sketched datapath for APU + wrote some RTL. Will do a code review for this with Ruslana next week and try a basic test on FPGA.

Summary of time spent this week

• CGB debugging: 9+ hrs
• I2S implementation: 2 hrs
• APU research + datapath + RTL: 4 hrs

Schedule / Progress

I believe I’m on schedule.  I don’t have any new concerns about the PPU or APU largely, but I should really integrate the PPU next week so I can debug some larger tests.

Next Step(s)

• DMG PPU integration.
• APU test on FPGA.

 

My goal(s) for this week were some subset of:

• Get DMG PPU integrated with CPU (if CPU gets integrated with memory)
• Fix scrolling / sprite bug in DMG PPU
• Debug CGB PPU
• Attempt to read from and write to WM8731 using i2c and get some confirmation that it was configured correctly.

Accomplished

DMG PPU (4-color PPU)

I fixed a few more bugs, and wrote a new testbench to do the equivalent of the dmg-acid2 test. Ruslana and I also performed a basic VGA test which was successful, and I have integrated the updated VGA logic with my PPU. 

CGB PPU (full-color PPU)

I propagated bug fixes from the DMG version to the CGB version. The CGB PPU now renders basic backgrounds with hardcoded color palettes.

APU / CODEC Research

I also implemented a basic test on the WM8731  by writing to the reset register. This test appears to be successful so I have implemented the full WM8731 configuration i2c logic to set 10+ registers and setup i2s communication.

Summary of time spent this week

• VGA test: 2 hrs
• WM8731 Reset test: 5 hrs
• WM8731 Full Configuration implementation + simulation debug: 8 hrs
• DMG debugging + CGB updates: 3 hrs

Schedule / Progress

Overall, I’m very much on schedule.  I don’t have any concerns regarding getting the full PPU working once we get everything integrated (as the PPU is fairly well tested in my opinion). The APU still remains a bit of a risk, however, using the CODEC directly now definitely seems viable.

Next Step(s)

• Validate full WM8731 configuration.
• Sketch I2S implementation (+ test with basic wave on FPGA).
• DMG PPU integration.
• CGB PPU debugging — target: get backgrounds and windows working.

Accomplished

My goal for this week (and break) was to mainly finish debug the PPU and get started on the full color implementation.

DMG PPU (4-color PPU)

• I spent most of my time this week on getting the DMG PPU fully functional—and I was pretty successful! I decided to rewrite the testbench so that it would also generate the final image (in PPM format) so I wouldn’t need to use a Python script. This sped-up my debugging progress considerably. 
• The other main breakthrough with debugging came in the form of SameBoy (GameBoy emulator), which I used to get the VRAM data and the OAM data for each frame. This method is not perfect as it doesn’t really give me information for crucial control registers that can change on a line by line basis. However, it helped me find many of the weirder bugs in my PPU a lot more quickly. 

  

• The DMG PPU is very close to being done. I still have minor issues with certain sprite and scrolling edge cases, however these frames (or sequence of frames) involve CPU writes to VRAM so I have no way of verifying if the issue is with my RTL or simply because I don’t have the perfect snapshot of the memory.
• In summary, I’m pretty happy with the progress and feel confident moving onto working on the full-color PPU. Here are some frames I rendered this week:

  

  

CGB PPU (full-color PPU)

I used the information I collected during the prior week to make the necessary updates for the full-color PPU. Because of my modular design of the rendering pipeline, I am able to make changes on the DMG PPU but still treat the layers as “black boxes” in some sense and extrapolate to make the CGB PPU integrated with larger memory sizes, many more color palettes and many new edge cases.

APU / CODEC Research

Given the NIOS / Quartus based roadblock we hit last week, I spent some time researching alternative solutions with Ruslana. The most promising approach is directly using the CODEC (WM8731) without using the NIOS softcore by configuring the registers on the WM8731 using i2c and then transferring the actual data using i2s. This appeared to be quite complex at first, especially because we weren’t able to find any evidence that someone else had managed to do this. But we’ve recently found some labs (form digital design classes at other universities who also using the same FPGA) that implement different fragments of the logic on the WM8731 directly.

I plan to use very simple i2c based test with the WM8731 to see if we get an ACK after a write to the reset register on WM8731. This should help us evaluate on the feasibility of using this approach for the APU.

Design Report

I also spent a decent chunk of time working on the design report the week it was due. We ended up working almost until the deadline as we received some crucial feedback from our design presentation somewhat late, but we were able to make the necessary updates before the deadline.

Summary of time spent (Week of 2/23 to 3/1):

• Researching how to use WM8731 (Audio CODEC on the DE2-115): 6 hrs
• Design Review Report: 8 hrs

Summary of time spent (Week of 3/2 to 3/8):

• Writing new testbench: 2 hrs
• PPU debugging + VGA testing : 12 hrs
• Full-color (CGB) implementation: 3 hrs
• Writing I2C based sound check test for the WM8731: 2 hrs

Schedule / Progress

Overall I’m on schedule or maybe slightly ahead as I feel relatively confident about the correctness of the DMG PPU (wrt to our MVP games — Tetris and Dr Mario should both be pretty much correct  as they have no scrolling).   I will also likely be spending some sizable amount of time on the APU from this week onwards as that remains as our largest unknown at the moment.

Next Step(s)

My goal(s) for next week are some subset of:

• Get DMG PPU integrated with CPU (if CPU gets integrated with memory)
• Fix scrolling / sprite bug in Pokemon Red:

• Debug CGB PPU
• Attempt to read from and write to WM8731 using i2c and get some confirmation that it was configured correctly.

Accomplished

My goal for this week was to debug the PPU and scope out what updates would be necessary for the full color implementation.

I continued unit testing the PPU and doing complete PPU level single frame and multi-frame tests. I was able to debug a majority of the single frame test cases, but I still have some bugs when rendering frames with more than one sprite. At the moment, I have not integrated the VGA controller logic to test with the FPGA, however, I have been debugging using a custom Python script to render a frame using a pixel array generated using the PPU’s Frame Buffer. Here’s a frame my PPU rendered:

Testing overall has still been a bit of a challenge because in the able of a memory controller and a CPU, my testbench has to be able to simulate the entire environment that the PPU requires. However, I think this is very much worth the effort, as it is likely to make debugging once the full system is integrated much easier. I also spent some time preparing for the Design presentation earlier this week as it was my turn to do the presentation.

Summary of time spent:

• PPU debugging + adding new tests to the testbench : 8 hr
• Full-color design updates research: 3 hr
• Presentation prep + peer review: 3 hr

Schedule / Progress

Overall I think I’m on schedule or slightly behind schedule because I am slightly behind schedule on debugging single frame tests but I started debugging some multi-frame tests and I’ve scoped out what updates/changes will be required for the full-color version. I anticipate that I will be able to get it working full by next weekend.

Next Step

My main goal for next week is to continue debugging the PPU and hopefully also test and profile my implementation a bit after integrating my code with the VGA logic required to test the PPU on the FPGA.

Accomplished

My goal for this week was to update the RTL for the PPU to work in accordance with the Memory Controller and testing my implementation so far.

I have unit tested a majority of the phases and more complex sections of my design like the object sorting, scrolling + window + background overlay logic, and switching between different modes, scanlines, and frames. I updated my testbench to include an end-to-end test for the PPU where I simulate the VRAM, OAM, control register reads and writes but I have not completed debugging the full design. At the moment, I have not gotten my hands on a DE2-115 FPGA so I haven’t been able to test the VGA controller logic on an FPGA, however, I wrote a Python script that uses a frame dump (2D pixel array) as an input and generates an image for debugging purposes.

I finished up the slides for the design presentation and updated it based on the feedback we got during our weekly meeting. I also spent some time preparing for the presentation next week.

Summary of time spent:

• PPU design updates based on Memory Controller: 2 hr
• Scoping cases to test + implementing testbench: 4 hr
• Integrating design part-by-part + debugging: 6 hr
• Presentation Slides + prep: 3 hr

Schedule / Progress

I am slightly ahead of schedule overall having already debugged majority of the individual components of the design. Integrating the phases, multiple state machines, and timing logic part by part lead me to spend more time writing the testbench than working on the design but I believe it sped up the debugging process overall quite a bit.

Next Step

My main goal for next week is to debug the PPU end-to-end and make any updates required for integration with the Memory Controller. I intend to hopefully test my PPU on the FPGA with the VGA Controller and be able to fully render a frame by end of next week.

Accomplished

My goal for this week was to finish my datapath for the PPU and get the RTL complete so I can begin testing next week.

I have completed the RTL and verified that my code is synthesizable. I tested some of the smaller modules dedicated to sprite searching and pixel/frame buffering. I have already started working on the testbench which is my main task for next week. I also helped Ruslana with research into some FPGA memory use questions.

I also spent some time this week working on the slides for the design presentation and did some research into effectively mapping out some of our qualitative use-case requirements to more testable quantitative design requirements.

Schedule / Progress

As I have already started working on the testbench and I am also almost done with my design presentation slides, I think that should put me well ahead of schedule at the moment.

Next Step

My main goal for next week is to debug as many single-frame rendering cases as time allows. I’ve mapped out about 20 different edge cases across sprite priority, sprite search, FIFO and memory related operations that need to be tested.  I expect this round of testing to be somewhat involved because my testbench needs to be able to simulate everything — memory, CPU updates to control registers, interrupt handling etc.

I also plan to finish up any updates to my design presentation slides based on feedback and start preparing for the actual presentation.