Posted on

Team Status Report for 4/26/25

Progress:

  • Tetris is playable, with fully working controller inputs, but runs at ~4* speed
  • Found a timer initialization and incrementation bug.

Risks and Risk Management:

  • FPGA debugging is a very “guess and hope for the best” process, even with signal-tap.

Tests:

  • CPU
    • Handmade test for every Gameboy instruction
    • Blarrg cpu-instrs tests run on CPU.
      • Fixed some misunderstandings of Gameboy specification details.
  • PPU
    • Basic static frames from Tetris/Dr. Mario with fixed tile/sprite preloaded memory
    • Dmg-Acid tests on Simulation
    • Basic static frames from MMU/CPU/PPU integration
  • MMU
    • Basic testbench checks on synchronous cycle BRAM accesses (R/W)
    • Synchronous cycle I/O registers (PPU/APU/Interrupt) (R/W)
    • Basic timer register checks
  • Simulation
    • Blarg cpu-instrs tests.
      • Many MMU bugs fixed
    • 1st pre-loaded frame of Tetris test.
    • 1st Tetris frame generation test.
      • 3 clocks were added to the design
      • CPU IME (interrupt enable) register misunderstanding fixed.
      • Many MMU bugs fixed
    • 1st, 2nd, 3rd frame + controller input test on Dr. Mario.
      • Fixed PPU palette issue
      • Joycon register spec misunderstanding fixed.
      • Many MMU bugs fixed
  • Physical
    • Basic controller button to LED test
    • DMG-Acid test rendering
      • Fixed jagged clock issues (ensured that clocks were derived off of others for adequate timing)
    • “Play” Dr. Mario.
      • Synthesis results in non-deterministic behavior.
    • Play Tetris
      • Joycon issue determined via patterns and fixed.
Posted on

Katherine’s Status Report for 4/26/25

Accomplished:

  • Found and fixed the bad controller input issue.
  • Verified lines will disappear in Tetris.
  • Found timer initialization and incrementation issues in the simulation.
  • Determined bank switching is required to play any part of Link’s Awakening/Pokémon
Next Step:
  • Continue debugging Tetris and Dr. Mario on hardware
  • Attempt other games to see if we can find more working games for the demo
  • Make aesthetic updates for the demo
Other Notes or Concerns:
  • All games are stuck in hard mode (runs at about 4* speed)
Posted on

Team Status Report for 4/19/25

Progress:

  • Tetris is playable, with bugs
    • Games run at double speed (but seemingly, this unfortunately is not tied to clock frequency or timer registers)
    • Joypad inputs don’t always get processed
  • Dr. Mario
    • Mario won’t toss his pill. We are suspicious of an HRAM or vblank handler interrupt routine error.
Design Changes:
  • Implemented Serial Transfer Control/Data Registers because Dr. Mario ROM polls from them

Risks and Risk Management:

  • FPGA debugging is a very “guess and hope for the best” process, even with signal-tap.
Posted on

Katherine’s Status Report for 4/19/25

Accomplished:

  • Debugged FPGA implementation with teammates
    • Tetris is playable, but glitchy
      • Runs at double speed.
      • Sometimes joypad inputs aren’t processed.
    • Dr. Mario doesn’t toss the pill.
Next Step:
  • Continue debugging Tetris and Dr. Mario on hardware
Other Notes or Concerns:
  • We found that recompiling will sometimes give us different results.
  • Debugging is really difficult, even with signal tap, often coming down to guessing and seeing if it works.

Tools/knowledge:

The major thing I had to learn was the Gameboy specification. Although there are some online resources, such as YouTube videos, fan-made documentation, Discord chats, Reddit posts, and software emulators, they are often incomplete or give false information. I had to cross-reference many of these sources to get the full picture. Discord was particularly helpful when learning how to get Verilog to read a .gb file.

Tool-wise, I had to learned how to set up very user-friendly scripts to simulate using free software called Modelsim, which is much more convenient and has more debugging tools than VCS.

Posted on

Katherine’s Status Report for 4/12/25

Accomplished:

  • Debbuged Tetris and Dr. Mario in simulation with teammates
    • Tetris reaches the first frame
    • Dr. Mario reaches the third frame
Dr.Mario — Frame 1
Dr. Mario — Frame 2
Dr. Mario — Frame 3
  • Debugged controller input in simulation with teammates
    • Was able to do multiple controller presses to access new screens in Dr. Mario
  • Debugged FPGA implementation with teammates
Next Step:
  • Work on debugging Tetris and Dr. Mario on hardware
Other Notes or Concerns:
  • FPGA tests do not match the simulation.
    • Proving to be very difficult to debug.
    • Signal taps and lights on FPGA are being used for visibility.
  • Verification and Validation discussion is in the team status report
Posted on

Team Status Report for 3/29/25

Progress:

  • Integration
    • MMU and CPU integration has been verified. All tests pass except interrupts (which we are debugging now that the PPU is introduced)
    • Testbench made for full integration
    • Full integration in progress
      • Working on generating a frame of Tetris
      • Working on debugging Acid tests
    • With initialized VRAM/OAM and a few hardcoded PPU registers, we managed to generate a tetris frame. This confirms that the PPU is accessing MMU correctly.

Image

  • I/O
    • New controllers have been assembled

ImageImage

Image
Posted on

Katherine’s Status Report for 3/29/25

Accomplished:

  • Verified MMU and CPU are integrated
  • Integrated all units
  • Made a testbench to test full integration
  • Started debugging all units with Tetris and dmg-acid-test
  • 2 new controllers created
Next Step:
  • Work on debugging Tetris
Other Notes or Concerns:
  • We are on schedule.
  • The blargg interrupt tests can’t be fully run due to timing optimizations done to the PPU. However, what was able to be run shows that interrupts will probably work.
  • Tetris is difficult to debug. To make debugging slightly easier, I am using the software emulator SameBoy to verify our implementation’s functionality.
Posted on

Team Status Report for 3/22/25

Progress:

  • Integration
    • MMU and CPU have been integrated
    • Testbench made for MMU and CPU integration
    • MMU and CPU integration debugging is in process.
  • PPU
    • CGB PPU debugging — backgrounds and windows works.
  • MMU
    • BRAM works in testbench
    • IO timer/apu/ppu/interrupt registers work in testbench
    • debugging DMA transfer details but CPU/MMU integration has begun
  • APU
    • Implemented I2S logic — works in simulation.
    • Sketched APU datapath + RTL.
  • I/O
    • New controller has been assembled
Design Changes:
  • Continuing along with clock at 2x CPU frequency for MMU, given that MMU BRAMs have to read out in 2 clock cycles (and we are expecting single cycle delay in CPU case)
Posted on

Katherine’s Status Report for 3/22/25

Accomplished:

  • Integrated the CPU and MMU
  • Made a testbench to test the CPU and MMU integration
  • Made another controller.
Next Step:
  • Debugging CPU MMU integration.
  • Integrate PPU.
Other Notes or Concerns:
  • Integration is happening later than expected, but it seems to be going smoothly so far.
Posted on

Katherine’s Status Report for 3/15/25

Accomplished:

  • Figured out how to read ROMs in System Verilog.
  • Made a testbench to run Blargg tests on the CPU.
  • Did the ethics assignment.
  • Debugged the CPU using Gameboy Doctor.
    • Passing all CPU Blargg tests except test 2.
Next Step:
  • Update controllers to use the new, thinner wires.
  • Integration.
Other Notes or Concerns:
  • Progress is on schedule.
  • Blargg test 2 (interrupts) requires integration with MMU and PPU.