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Team Status Report 2/15/25

Progress:

  • CPU:
    • Multicycle CPU framework completed
    • Instructions implemented: 11
    • Instruction tests written: 23
  • PPU
    • RTL updated based on Memory organization / controller related design updates.
    • Implemented testbench, Python script to render image based on frame dump.
    • Unit tested most of the design and parts of the integrated logic. Working on debugging the PPU with a full end-to-end test.
  • MMU
    • Re-designed memory controller to utilize FPGA Block RAMs instead of DE II SRAM/SDRAMs for simplicity of integration
    • Synthesized and tested Block Rams of different sizes (in ROM and RAM variant) and confirmed that they work
    • Creating Memory Controller according to updated spec (DMA support)
  • Other I/O
    • Did research into USB/Audio integration. Discovered that NIOS II cannot be used,  but there are IPs provided by Altera that use an Avalon master/slave interface.
    • Learned more about the Quartus Avalon Slave Interface, currently working to create unit tests
Design Changes:
  • Swapped to cycle-accurate multicycle CPU.
  • Reworked DMA responsibility

Risks and Risk Management:

  • Many CPU instructions are listed as TODO in “Gameboy: Complete Technical Reference”
    • Will look at Intel 8080 and software emulators to fill in the blanks.

Part A – Katherine (public health, safety or welfare):

Our Gameboy will be made as a larger system, similar to a desktop computer, with a larger screen and controller. This will help reduce eye strain, making it easier for users to play games, especially for those with visual impairments. The larger controller will also improve accessibility for people with limited mobility. These modifications will make gameplay less physically taxing, hence improving overall safety.

Part B – Ruslana (social factors):

Our capstone responds to social factors because we intend to make playing the Gameboy an all-inclusive experience at demo day, where anybody can go and engage with the video games. Furthermore, we are preserving the Gameboy’s heritage and legacy by showing others the original and first console ever made that has paved the way for modern ubiquitous consoles all around us today (such as the Switch, Playstation, Xbox, etc.). People who have experienced the original Gameboy and curious younger generations can be both entertained and learn about our hardware implementation for this project.

Part C – Bharathi (economic factors):

Our project offers a cost-effective and sustainable way to preserve and play retro games without relying on original hardware which can be difficult to find, maintain, or upgrade. Unlike a single-purpose handheld console, our FPGA-based design can be upgraded and modified over time without additional hardware costs. Our project also encourages the digital distribution and consumption of retro games through legally obtained ROMs, reducing need for physical cartridges that may become may be hard to find / use.

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Bharathi’s Status Report for 2/15/25

Accomplished

My goal for this week was to update the RTL for the PPU to work in accordance with the Memory Controller and testing my implementation so far.

I have unit tested a majority of the phases and more complex sections of my design like the object sorting, scrolling + window + background overlay logic, and switching between different modes, scanlines, and frames. I updated my testbench to include an end-to-end test for the PPU where I simulate the VRAM, OAM, control register reads and writes but I have not completed debugging the full design. At the moment, I have not gotten my hands on a DE2-115 FPGA so I haven’t been able to test the VGA controller logic on an FPGA, however, I wrote a Python script that uses a frame dump (2D pixel array) as an input and generates an image for debugging purposes.

I finished up the slides for the design presentation and updated it based on the feedback we got during our weekly meeting. I also spent some time preparing for the presentation next week.

Summary of time spent:

  • PPU design updates based on Memory Controller: 2 hr
  • Scoping cases to test + implementing testbench: 4 hr
  • Integrating design part-by-part + debugging: 6 hr
  • Presentation Slides + prep: 3 hr

Schedule / Progress

I am slightly ahead of schedule overall having already debugged majority of the individual components of the design. Integrating the phases, multiple state machines, and timing logic part by part lead me to spend more time writing the testbench than working on the design but I believe it sped up the debugging process overall quite a bit.

Next Step

My main goal for next week is to debug the PPU end-to-end and make any updates required for integration with the Memory Controller. I intend to hopefully test my PPU on the FPGA with the VGA Controller and be able to fully render a frame by end of next week.

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Bharathi’s Status Report for 2/8/25

Accomplished

My goal for this week was to finish my datapath for the PPU and get the RTL complete so I can begin testing next week.

I have completed the RTL and verified that my code is synthesizable. I tested some of the smaller modules dedicated to sprite searching and pixel/frame buffering. I have already started working on the testbench which is my main task for next week. I also helped Ruslana with research into some FPGA memory use questions.

I also spent some time this week working on the slides for the design presentation and did some research into effectively mapping out some of our qualitative use-case requirements to more testable quantitative design requirements.

Schedule / Progress

As I have already started working on the testbench and I am also almost done with my design presentation slides, I think that should put me well ahead of schedule at the moment.

Next Step

My main goal for next week is to debug as many single-frame rendering cases as time allows. I’ve mapped out about 20 different edge cases across sprite priority, sprite search, FIFO and memory related operations that need to be tested.  I expect this round of testing to be somewhat involved because my testbench needs to be able to simulate everything — memory, CPU updates to control registers, interrupt handling etc.

I also plan to finish up any updates to my design presentation slides based on feedback and start preparing for the actual presentation.

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Introduction and Project Summary

Emulators play a crucial role in preserving the history of video games, allowing players to continue enjoying classic titles on modern hardware long after original devices have been discontinued or become obsolete. The goal of our project is to develop an FPGA-based GameBoy emulator that runs GameBoy ROMs, incorporating essential subsystems such as the CPU, Memory Mapping Unit (MMU), Pixel Processing Unit (PPU), Audio Processing Unit (APU), and input/output drivers with controller support. The system will provide VGA video output and, at a minimum, be able to run iconic games like Tetris and Dr. Mario, faithfully recreating the original GameBoy experience.

Through this project, we aim to preserve the legacy of retro gaming while showcasing the technological progress in both hardware and software that has shaped the gaming industry, helping to inform the development of future gaming hardware and software optimizations. Replicating older systems also allows future game developers to understand how past have technologies shaped modern gaming devices, while also offering insights into how current hardware and software can be improved for newer architectures.