Mostly all included in team update list.
- Debugging FPGA with the rest of team
- Learned how to use SignalTap to focus on probing CPU register values/Interrupt register values, but it’s been slow
- Resynthesizing design gives different behavior, which is worrying, but our design is also quite sensitive to change right now (we attempted to refactor to eliminate X’s and this caused some new frame artifacts to show up)
- Hoping to fix immediate issue with double speed and pill
Learned things:
- Learned about NIOS II processor and how complicated altera toolchain is
- Learned about signal tapping to debug on FPGA
- Learned about dealing with multiple clocks on design
- Learned from my partners about how to tackle large scale combinational loops in a pragmatic manner
- Learned about modelsim
- Learned about memory interfaces and communication protocols (to SDRAM, SRAM, Audio CODEC), though we haven’t been able to utilize it so much for our project
Most of this came from trial and error + scouring the internet.