Progress:
- Integration
- MMU and CPU integration has been verified. All tests pass except interrupts (which we are debugging now that the PPU is introduced)
- Testbench made for full integration
- Full integration in progress
- Working on generating a frame of Tetris
- Working on debugging Acid tests
- With initialized VRAM/OAM and a few hardcoded PPU registers, we managed to generate a tetris frame. This confirms that the PPU is accessing MMU correctly.
- I/O
- New controllers have been assembled
