- Went through MMU code review with Katherine/Bharathi. Reevaluated some interrupt routine code and corrected it accordingly
- Created python script for acquiring .mif files when given a binary ROM obtained from online
- Created basic testbench for MMU to stress memory r/w, IO r/w routines.
- Testbenching MMU and verifying:
- basic memory cpu/ppu read/writes to all BRAMS(ROM, VRAM, EXRAM, WRAM, OAM, HRAM)
- basic cpu IO read/writes (timer registers, APU registers, PPU registers, interrupt registers)
- DMA transfer during hblank/vblank works without interfering with the above
- Currently, basic BRAM tests to each memory unit are good for all ppu modes.
- Currently waveforming and debugging IO integration (timer registers are working, still need to verify the rest)
Remarks:
I’m confident that integration can start by next week, because I am developing high confidence in the Memory Controller being ok-enough for talking to the CPU. The edge cases can be caught during actual execution. I caught a lot of erroneous behavior with my personal testbench, but it’s still a model of what I expect the communication to be based off on Pandocs, not the actual ROM’s behavior.