Progress:
- CPU:
- All memory instructions completed
- Instructions implemented: 26
- Instruction tests written: 40
- PPU
- Single frame test debugging mostly done (still debugging testcases with more than one sprite)
- Debugging multi-frame rendering test
- Scoping full-color PPU design updates
- MMU
- Created several Altera MM modules that were able to be placed in Qsys Platform Designer, and routed to the SRAM controller and other interfaces
- Other I/O
- Spent a lot of time researching USB integration
Design Changes:
- After evaluating the Cypress USB Controller, the decision was made to pivot to the Raspberry Pi GPIO approach as a backup plan, while exploring the synthesis of the NIOS II soft core CPU for improved integration
Risks and Risk Management:
- The main risks involve the trial-and-error nature of writing a custom RTL unit for USB communication and potential resource limitations with the NIOS II soft core CPU consuming LUTs