- Spent a lot of time researching USB integration again
- Tore through Altera Memory Mapped Interfaces for Master/Slave, seems feasible to integrate with SRAM Controller. Less worried about that integration.
- Created several Altera MM modules that were able to be placed in Qsys Platform Designer, and routed to the SRAM controller and other interfaces
- Qsys (platform designer) allows individual IPs to be layed out along with Avalon IPs, and the interconnect logic gets automatically generated
- Looked through on chip Cypress USB Controller and realized it had to use NIOS II soft core cpu to communicate, other forms of communication would be our own version of writing a USB OTG Controller to interface with it
- All altera examples involved declaring the NIOS II soft core cpu on the FPGA (thereby using up LUT resources)
- And also writing USB driver code in C to support talk to the USB peripheral. This seemed tedious at first.
- After many hours of research for documentation, results on the doc were sparse. Although writing a custom RTL unit to communicate to Cypress doesn’t seem impossible, it would involve trial & error and a lot of stabbing at a black box.
Therefore, I’m pivoting to trying the Raspberryp Pi GPIO route as a back up plan, but also trying to synthesize part of the NIOS II soft core CPU. This may also enhance integration with the audio CODEC as well, because the Wolf chip has a similar problem.