Progress:
- CPU:
- All frameworks completed.
- Instruction buffer added.
- Instructions implemented: 2
- PPU
- RTL completed based on datapath.
- Testbench development in progress.
- MMU
- Re-designed memory controller to utilize FPGA Block RAMs instead of DE II SRAM/SDRAMs for simplicity of integration
- Synthesized and tested Block Rams of different sizes (in ROM and RAM variant) and confirmed that they work
- Other I/O
- Did research into USB/Audio integration. Discovered that NIOS II cannot be used, but there are IPs provided by Altera that use an Avalon master/slave interface.
Design Changes:
- Swap to 32-bit word memory is under consideration.
- Swapped memory units for BRAM
Risks and Risk Management:
- If a swap to 32-bit words is confirmed, a full reworking of the instruction buffer will be required.
- CPU will be developed with the assumption of 16-bit words until told otherwise since the 16-bit word architecture is harder to implement.
- To make the possible transition easier, we will mark all code that must be removed or replaced if this change occurs.
- Memory has been tested but I/O parts still need to be confirmed ASAP.