Ruslana’s Status Report for 2/8/25

Researched memory options on FPGA DE 2 board (block rams, SDRAM, SRAM, Flash) and explored options through Quartus Megawizard IP Interface
Discussed with Professor Nace for potential options on FPGA memory
Derived new design based on FPGA Block RAMs based on discussion with Bharathi and Katherine on CPU/PPU accesses
Re-designed Memory Controller Datapath to utilize block RAMS
Obtained DE II 115 boards from Quinn and distributed it to members
Created 5 generic memory modules for Block RAM
Created testbench for each memory module in simulation and Chip Interface
Synthesized and tested BROMs/BRAMs on FPGA and confirmed success by empirical validation
Did research into audio/USB integration and realized NIOS II is a soft-core processor that you can write C code for, but it gets synthesized onto the FPGA and uses up the LUTS. It’s a way to give people an easy route to write C code to be used on FPGA, but not on on-chip computer that talks to the FPGA itself.
- FPGA University Program on Quartus ECE Machines gives some kind of Qsys interface to create USB and Audio IP devices? Requires further research.