Accomplished
My goal for this week was to finish my datapath for the PPU and get the RTL complete so I can begin testing next week.
I have completed the RTL and verified that my code is synthesizable. I tested some of the smaller modules dedicated to sprite searching and pixel/frame buffering. I have already started working on the testbench which is my main task for next week. I also helped Ruslana with research into some FPGA memory use questions.
I also spent some time this week working on the slides for the design presentation and did some research into effectively mapping out some of our qualitative use-case requirements to more testable quantitative design requirements.
Schedule / Progress
As I have already started working on the testbench and I am also almost done with my design presentation slides, I think that should put me well ahead of schedule at the moment.
Next Step
My main goal for next week is to debug as many single-frame rendering cases as time allows. I’ve mapped out about 20 different edge cases across sprite priority, sprite search, FIFO and memory related operations that need to be tested. I expect this round of testing to be somewhat involved because my testbench needs to be able to simulate everything — memory, CPU updates to control registers, interrupt handling etc.
I also plan to finish up any updates to my design presentation slides based on feedback and start preparing for the actual presentation.