This week, we have made good progress on both the embedded and Verilog side. One significant risk is that our peripheral components will not be compatible with the FPGA, which will be difficult to fix once they are solidified on the PCB. We are managing this by testing and researching these components beforehand, such as the microSD card reader. This way, we can change or find new components before we get the PCB fabricated. This has led to a possible change, since we have ordered two different microSD card readers out of concern that the original one won’t be compatible with the FPGA’s 3.3V logic. Once the microSD cards come in, we can verify if we can move forward with this option. Other than that, no changes to the existing design have been made this week.
Another risk is that the individual RTL components will not integrate properly. We are mitigating this by testing the integration of individual modules after they are individually validated. This is the current phase we are in for the RTL, since Amelia has validated that the PS/2 works in simulation and synthesis, the encryption in simulation, and the PS/2 and encryption together in simulation. However, we have not yet succeeded in integration the PS/2 and encryption in synthesis, and is what we will be working towards this week.