Week 4
It is possible that with the base Jetson Nano setup, we may not be able to meet the latency requirements. For this, our contingency plan is to use the CUDA kernels given to us and write optimized code to meet requirements. Also, we plan to use an FPGA to accelerate some of the ML operations in the Jetson, but if the I/O speeds prove to be too slow, and we meet specs without the FPGA, then we will simply not use it. We did not make any major modifications to our initial ideas this week; however we did brainstorm for additional functionalities that we might want to add if time and resources permit. The schedule has not been updated.