{"id":253,"date":"2024-04-21T04:09:59","date_gmt":"2024-04-21T04:09:59","guid":{"rendered":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/?p=253"},"modified":"2024-04-21T04:09:59","modified_gmt":"2024-04-21T04:09:59","slug":"andrews-status-report-for-april-20","status":"publish","type":"post","link":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/2024\/04\/21\/andrews-status-report-for-april-20\/","title":{"rendered":"Andrew’s Status Report for April 20"},"content":{"rendered":"

Personal tasks of this week:<\/strong><\/p>\n

Task:<\/strong>\u00a0Finalize circuit design and layout<\/p>\n

Definition:<\/strong>\u00a0Finalize the design of the circuit and the layout of the PCB so it can be ordered.<\/p>\n

Completion:<\/strong> The task is\u00a0partially completed<\/em>. All of the schematics are completed and verified with LTSpice to work. Furthermore, we designed and implemented the digipot calibration method, as well as the protocool we will be using for the pcb. As for layout, there has been some significant progress in figuring out the majority of the connections, but the final layout still needs to be completed.<\/p>\n

\"\"<\/a>\"\"<\/a>\"\"<\/a><\/p>\n

Next Steps:<\/strong><\/p>\n

My next step is to finish the layout of the PCB<\/p>\n

Overall progress assessment:<\/strong><\/p>\n

My progress is somewhat behind\u00a0schedule<\/em>, because the PCB is not yet ready to be ordered.<\/p>\n

Learning to use new tools:<\/strong><\/p>\n

A new tool I had to learn was LTSpice, which is a circuit simulation software for circuit analysis and simulation. I learned how to use it by looking at tutorials to figure out what was going on and import parts, then figured out the rest from there while looking up specific tools like simulation up.<\/p>\n","protected":false},"excerpt":{"rendered":"

Personal tasks of this week: Task:\u00a0Finalize circuit design and layout Definition:\u00a0Finalize the design of the circuit and the layout of the PCB so it can be ordered. Completion: The task is\u00a0partially completed. All of the schematics are completed and verified with LTSpice to work. Furthermore, we designed and implemented the digipot calibration method, as well … <\/p>\n

Continue reading “Andrew’s Status Report for April 20”<\/span><\/a><\/p>\n","protected":false},"author":824,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[1],"tags":[],"_links":{"self":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/posts\/253"}],"collection":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/users\/824"}],"replies":[{"embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/comments?post=253"}],"version-history":[{"count":1,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/posts\/253\/revisions"}],"predecessor-version":[{"id":257,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/posts\/253\/revisions\/257"}],"wp:attachment":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/media?parent=253"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/categories?post=253"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s24-teamd6\/wp-json\/wp\/v2\/tags?post=253"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}