What are the most significant risks that could jeopardize the success of the<\/b><\/p>\n
project? How are these risks being managed? What contingency plans are ready?<\/b><\/p>\n
The most significant risk right now is the encoder side. As mentioned in Michael\u2019s status report, there are severe constraints on what we can do on the encoder side due to the need to use the PSRAM module on the ESP32. The PSRAM module\u2019s 40 MB\/s is a hard limit that is hard for us to work around. Being one of the first stages of the pipeline means that any changes in the encoder side will trickle down and cause issues for the central receiving node and the FPGA decoder. Current contingency plans in case this PSRAM issue does materialize is to set the encoder at a lower quality which will minimize the amount of data that needs to be processed by the LWIP and Wi-Fi stacks. The reduced workload will in turn alleviate the pressure on the PSRAM module.<\/span><\/p>\n <\/p>\n Were any changes made to the existing design of the system (requirements,<\/b>block diagram, system spec, etc)? Why was this change necessary, what costs\u00a0<\/b>does the change incur, and how will these costs be mitigated going forward?<\/b><\/p>\n No changes<\/span><\/p>\n","protected":false},"excerpt":{"rendered":" What are the most significant risks that could jeopardize the success of the project? How are these risks being managed? What contingency plans are ready? The most significant risk right now is the encoder side. As mentioned in Michael\u2019s status report, there are severe constraints on what we can do on the encoder side due … <\/p>\n