{"id":75,"date":"2023-02-18T22:04:03","date_gmt":"2023-02-18T22:04:03","guid":{"rendered":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/?p=75"},"modified":"2023-02-18T22:04:03","modified_gmt":"2023-02-18T22:04:03","slug":"anju-itos-status-report-for-2-18-2023","status":"publish","type":"post","link":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/2023\/02\/18\/anju-itos-status-report-for-2-18-2023\/","title":{"rendered":"Anju Ito&#8217;s Status Report for 2\/18\/2023"},"content":{"rendered":"<ul>\n<li>This Week\n<ul>\n<li>Tested speed of FPGA I\/O pins from the Dev board to see how fast communication can go from custom PCB to the FPGA\n<ul>\n<li><strong>Measured that 12.5MHz clock can cleanly be measured from the GPIO pins. From this, we decided that using an FPGA dev board was sufficient and a better option than a microcontroller.<\/strong>\u00a0Faster speeds yielded questionable results, although there is a possibility that the oscilloscope probes couldn&#8217;t measure as fast. We can safely rely on using the 12.5MHz clock (i.e. 25 Mbps) communication for our project.<\/li>\n<li>FPGA Spec\n<ul>\n<li>50MHz clock<\/li>\n<li>3.3V active\u00a0 high from GPIO pins\u00a0<img decoding=\"async\" loading=\"lazy\" class=\"size-medium wp-image-101 aligncenter\" src=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/FPGA_Oscilloscope-300x225.jpg\" alt=\"\" width=\"300\" height=\"225\" srcset=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/FPGA_Oscilloscope-300x225.jpg 300w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/FPGA_Oscilloscope-768x575.jpg 768w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/FPGA_Oscilloscope-1024x767.jpg 1024w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/FPGA_Oscilloscope.jpg 1170w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/li>\n<\/ul>\n<\/li>\n<li>Detailed measurements:\n<ul>\n<li>4.15MHz from FPGA, measured with an oscilloscope at 500MS\/s sampling:\n<ul>\n<li>3.28V high, 0.096V low<\/li>\n<li>0.192V (3.472V) overshoot, 0.096V undershoot (3.184V)<\/li>\n<li>Rise time: 4.6ns<\/li>\n<li>Fall time: 4.0ns<img decoding=\"async\" loading=\"lazy\" class=\"size-medium wp-image-102 aligncenter\" src=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/4Mbps-300x225.jpg\" alt=\"\" width=\"300\" height=\"225\" srcset=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/4Mbps-300x225.jpg 300w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/4Mbps-768x575.jpg 768w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/4Mbps-1024x767.jpg 1024w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/4Mbps.jpg 1170w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/li>\n<\/ul>\n<\/li>\n<li>With 6.25MHz, 200MS\/s sampling:\n<ul>\n<li>3.24V high, 0V low<\/li>\n<li>0.52V overshoot (3.76V, 3.24V base), 0.34V undershoot (2.9V)<\/li>\n<li>Rise time: 9.0ns<\/li>\n<li>Fall time: 8.75ns<img decoding=\"async\" loading=\"lazy\" class=\"size-medium wp-image-104 aligncenter\" src=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/6.25MHz-300x225.jpg\" alt=\"\" width=\"300\" height=\"225\" srcset=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/6.25MHz-300x225.jpg 300w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/6.25MHz-768x575.jpg 768w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/6.25MHz-1024x767.jpg 1024w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/6.25MHz.jpg 1170w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/li>\n<\/ul>\n<\/li>\n<li>With 12.5MHz, 500MS\/s sampling\n<ul>\n<li>Very clean signal<\/li>\n<li>Delta t = 12.5MHz<\/li>\n<li>0.200V overshoot, 0.12V undershoot<\/li>\n<li>Rise Time: 4.4ns<\/li>\n<li>Fall Time: 3.8ns<img decoding=\"async\" loading=\"lazy\" class=\"size-medium wp-image-105 aligncenter\" src=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/12.5MHz-300x225.jpg\" alt=\"\" width=\"300\" height=\"225\" srcset=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/12.5MHz-300x225.jpg 300w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/12.5MHz-768x575.jpg 768w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/12.5MHz-1024x767.jpg 1024w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/12.5MHz.jpg 1170w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/li>\n<\/ul>\n<\/li>\n<li>25MHz, 500MS\/s\n<ul>\n<li>Start to observe unclean signals<img decoding=\"async\" loading=\"lazy\" class=\"size-medium wp-image-106 aligncenter\" src=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/25MHz-300x225.jpg\" alt=\"\" width=\"300\" height=\"225\" srcset=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/25MHz-300x225.jpg 300w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/25MHz-768x575.jpg 768w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/25MHz-1024x767.jpg 1024w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/25MHz.jpg 1170w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/li>\n<\/ul>\n<\/li>\n<li>50MHz<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p><img decoding=\"async\" loading=\"lazy\" class=\"size-medium wp-image-103 aligncenter\" src=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/50MHz-300x225.jpg\" alt=\"\" width=\"300\" height=\"225\" srcset=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/50MHz-300x225.jpg 300w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/50MHz-768x575.jpg 768w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/50MHz-1024x767.jpg 1024w, http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-content\/uploads\/sites\/232\/2023\/02\/50MHz.jpg 1170w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/p>\n<ul>\n<li style=\"list-style-type: none\">\n<ul>\n<li>Worked with Roger and KJ to\u00a0come up\u00a0with communication protocol.\n<ul>\n<li>We weighed the different options between a SPI-based and a UART-based protocol, and concluded that <strong>we will use a UART-based protocol for LaserDrop,<\/strong>\u00a0as this would yield better results after evaluating it while thinking about sampling speed from FPGA, circuit response, etc.<\/li>\n<li>Decided on the packet properties of the laser communication (start sequence, packet ID, data, Hamming encoding, packet size)<\/li>\n<li>Decided which aspects of our project (CPU, FPGA, circuits, COTS IC) would handle which part of the protocol<\/li>\n<li>Came up with an error handling mechanism for lost packets<\/li>\n<li>Came up with a handshaking mechanism for beginning\/end of instantiating a communication<\/li>\n<\/ul>\n<\/li>\n<li>Designed the FPGA block diagram\u00a0that would handle this communication.\n<ul>\n<li>Overall FSM and block diagram that will interface with the FTDI chip and PCB circuitry.<\/li>\n<\/ul>\n<\/li>\n<li>Worked on the design review presentation with the whole group.<\/li>\n<\/ul>\n<\/li>\n<li>Schedule\n<ul>\n<li>My work is on schedule. My goal last week was to test whether the FPGA dev board or the microcontroller would be able to support the communication, which I was able to do. Due to the success of how fast the signals came across from the FPGA board, we concluded that a microcontroller would be unnecessary and we can go forth with a custom PCB that would interface with the FPGA.<\/li>\n<\/ul>\n<\/li>\n<li>Goal for next week\n<ul>\n<li>Practice and present the design review during class.<\/li>\n<li>Address the feedback\/concerns that we receive during the design review from the advisors, faculty, and classmates<\/li>\n<li>Refine and come up with a detailed FSM\/block diagram of the whole system<\/li>\n<\/ul>\n<\/li>\n<li>Principles\/Courses Used\n<ul>\n<li>18-240, 18-341: In these classes, I learned how to use and design the FPGA boards (Altera DE0-CV), which I used to think about how the FPGA will interface with the FTDI chip and PCB circuits and handle the protocol that we designed. In addition, protocols such as the Hamming encoding and USB were explored in these classes that helped when we were coming up with the communication protocol. In addition, I wrote simple SystemVerilog code to test out the FPGA speeds, which I will heavily use later on in this project as well.<\/li>\n<li>18-349: Embedded Systems taught about various protocols such as SPI, UART, and I2C that we thought through while coming up with our custom protocol. In addition, 18-100 and Manchester encoding, etc. were another features that we thought about when thinking about the communication protcol.<\/li>\n<li>MoonRanger (16-861\/16-865: Space Robotics): Gave me hands-on experience with communication protocols (UART, etc.) that helped during protocol design. In addition, I learned and often used oscilloscopes and other tools, which made it easy for me to figure out the FPGA speeds.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>This Week Tested speed of FPGA I\/O pins from the Dev board to see how fast communication can go from custom PCB to the FPGA Measured that 12.5MHz clock can cleanly be measured from the GPIO pins. From this, we decided that using an FPGA dev board was sufficient and a better option than a &hellip; <\/p>\n<p class=\"link-more\"><a href=\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/2023\/02\/18\/anju-itos-status-report-for-2-18-2023\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;Anju Ito&#8217;s Status Report for 2\/18\/2023&#8221;<\/span><\/a><\/p>\n","protected":false},"author":673,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[5],"tags":[3],"_links":{"self":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/posts\/75"}],"collection":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/users\/673"}],"replies":[{"embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/comments?post=75"}],"version-history":[{"count":3,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/posts\/75\/revisions"}],"predecessor-version":[{"id":108,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/posts\/75\/revisions\/108"}],"wp:attachment":[{"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/media?parent=75"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/categories?post=75"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s23-teamb5\/wp-json\/wp\/v2\/tags?post=75"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}