Roger Lacson’s Status Report for 4/8/2023

  • Personal Accomplishments
    • I was able to finish the hamming encoding updates and was able to present these updates at demo day. In terms of structure, Anju and I decided on sending 1024 bytes per packet. Out of these 1024 bytes, 4 are for start bytes, 4 are for the tag ID, and I have now decided to have 1008 bytes to send 693 bytes-worth of data (with the remaining 1024 – 4 -4 – 1008 = 8 bytes of data as padding). The 1008 bytes will consist of 504 2-byte hamming encoded bits. Each 2-byte portion has 11 bits-worth of the raw data that are hamming encoded to 16 bits. I modularized my code, starting with bit manipulation functions (get_ith_bit and set_ith_bit), then the (16,11) hamming encoding function, a function that would take 693 bytes of raw data and hamming encode it into a 1008 byte data packet, and then a function to read a file and then hamming encode all the data. Similarly for the receiver, I added a (16,11) hamming decoder and error corrector/detector, and a full-data decoder.
    • I created a test suite for my code. I tested each function individually from the lower-level code (bit manipulation) to the higher-level functions that code/decode entire files. To test the higher-level functions, I encoded files in a directory and decoded them, writing the result to a new file. I use diff to check if the files are equivalent. I then proceed to inject the hamming encoded bytes of files with one-bit errors and decode them to see if the one-bit error correction works properly. I then inject another error which should lead to the file being added into the error queue. I had all this working and verified on demo day.
    • I also wrote a simple script to send and receive bytes via laser using the D2XX library for demo day. This code was able to read and write bytes properly on demo day, although the laser itself needed precise alignment to have them work. There is an issue that when there is a read error, the chip does not continue to receive instructions from my laptop, which I need to figure out.
  • Schedule
    • I am currently still behind schedule according to the original plan, although I should still be able to complete the entire interface code by the end of this week to begin full integration once the board has been properly set and the FPGA is ready. I will aim to finish coding the entire sending and receiving codebase to program the boards to properly send or receive at any given time.
  • Deliverables
    • Code to properly control the FTDI/FPGA regarding implementing the protocol, sending/receiving data, and coding/decoding data.
    • Testing with the hardware and debugging my code/hardware setup based on performance (I do not have many means to test my code other than directly with the hardware).

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