![\"\"](\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s22-teame1\/wp-content\/uploads\/sites\/203\/2022\/02\/Board-300x225.jpg\")
<\/p>\nBasically, much of this week was spent realizing that Vitis has been broken on the ECE machines since the start of the new year. Basically, the very same Y2K22 bug that plagued Microsoft Exchange was affecting the build process for compiling to hardware on Vitis. Unfortunately, this took a bit of dredging to find on the Vitis forums, and so we lost a couple days of progress, as we thought that it was an issue with our personal configuration rather than an issue with the system itself. Thankfully, after pointing out the issue to Professor James Hoe, he was able to quickly implement the patch for fixing the build tools. Finally, we were able to compile a project and generate a PetaLinux image to flash onto the FPGA. But then we needed to actually interface with the FPGA. Unfortunately, due to some weird configurations, the FPGA\u2019s internal WiFi was not automatically set up, so we needed to interface with it through mouse and keyboard (we were also missing the mini Displayport cable, so we had to overnight that).<\/p>\n
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After finally gaining access to the FPGA interface, we were able to connect the Ultra96 to our local Router. Now, we are able to remote into the FPGA whenever we are connected to the local Router. We\u2019ll still need to do some poking around in order to gain access to the FPGA when on campus, as our apartment network does not play nicely with port forwarding, but I\u2019m sure we can figure something out. Either way, this is a good start for having a more streamlined development platform. We might decide to set up the board\u00a0 in 1307, so we can just VPN in, but it\u2019s flexible.<\/p>\n
![\"\"](\"http:\/\/course.ece.cmu.edu\/~ece500\/projects\/s22-teame1\/wp-content\/uploads\/sites\/203\/2022\/02\/Remote-300x157.png\")
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Other than this, we did some speicifc code analysis on the fluids.cpp file, but we\u2019ll talk more about this in the team report.<\/p>\n
Next week, my main goal is to compile a baseline kernel of the step2 function (which consists of the main body of the fuild simulation compuational kernel) using Vitis HLS. This will involve significant tinkering of the code and perhaps refactoring into more friendly datatypes. The best case scenario is that everything just compiles, but that\u2019s likely quite the pipe dream.<\/p>\n
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<\/p>\n","protected":false},"excerpt":{"rendered":"
Basically, much of this week was spent realizing that Vitis has been broken on the ECE machines since the start of the new year. Basically, the very same Y2K22 bug that plagued Microsoft Exchange was affecting the build process for compiling to hardware on Vitis. Unfortunately, this took a bit of dredging to find on … <\/p>\n