I spent 8 hours a day from Wednesday to Wednesday (got COVID at the beginning of break but was more or less asymptomatic so was quarantining for a week and a half with nothing to do). I finished the assembler then wrote all the unit tests in AGC assembly (with the exception of the IO stuff) I then wrote the entirety of our header file wrote the entire pipeline and decoder in SystemVerilog and wrote many of the sub-units (branching unit, stalling unit ect.) In doing all of this I caught issues with our design and that changed our pipeline design and got a better understanding of what some of the instructions do that I previously did not fully understood.<\/p>\n
I am well ahead of schedule. However as I will have more time (especially from break) the last couple of weeks compared to future weeks. Next week I hope to get the pipeline working and running the tests without failing. However that is probably a bit ambitious of a goal for one week (I also need to catch up on some of the classes I missed last week).<\/p>\n","protected":false},"excerpt":{"rendered":"
I spent 8 hours a day from Wednesday to Wednesday (got COVID at the beginning of break but was more or less asymptomatic so was quarantining for a week and a half with nothing to do). I finished the assembler then wrote all the unit tests in AGC assembly (with the exception of the IO … <\/p>\n