I neglected to post the last couple of weeks, but most of my tasks have been long-term anyways.\u00a0 I wrote the initial implementations of our CPU’s register file, arithmetic logic unit, memory address translation unit, and I\/O unit a few weeks back.\u00a0 Since then, a number of bugs with those units as well as the lower level computational units have been detected and addressed.\u00a0 With our interim demo quickly approaching, I’ve started to run basic tests using simple assembly programs written by Christopher, each testing a specific subset of our instruction set.\u00a0 Along with simple visual scans of Verilog implementations, a number of larger functional bugs have been identified and resolved.\u00a0 As of now, basic arithmetic appears to be working fine, as well as memory loads and stores.\u00a0 I plan to move on to writing test assembly programs for I\/O instructions in anticipation of the interim demo.\u00a0 Following that, I will begin implementing the I\/O<->serial interface units.<\/p>\n","protected":false},"excerpt":{"rendered":"
I neglected to post the last couple of weeks, but most of my tasks have been long-term anyways.\u00a0 I wrote the initial implementations of our CPU’s register file, arithmetic logic unit, memory address translation unit, and I\/O unit a few weeks back.\u00a0 Since then, a number of bugs with those units as well as the … <\/p>\n