This week, my main task was to create the memory mapped I\/O necessary to send controller input from the FPGA to the ARM core. In our design, we chose to use the lightweight AXI bus of the Cyclone V FPGA to accomplish this. Additionally, I set up my FPGA with a linux image that allows for a UART console and wrote a brief controller read program to test the communication. Finally, I set up an ARM cross-compilation development environment on my computer, using the arm-none-linux-gnueabihf library provided by arm, in order to compile the controller test program.<\/p>\n
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Under the current settings, the controller input is available to the ARM core at the base address of the lightweight AXI memory mapped I\/O space (address 0xFF200000). The controller test uses \/dev\/mem to mmap this address into its address space and read from it, then prints the results to the console.<\/p>\n
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Due to my unfamiliarity with qsys, the process of bringing up this communication took longer than I expected. When all was said and done, I did manage to get communication working, though I ran out of time and was unable to finish the controller section of our interface (which would require wrapping it in a kernel module which has a call safely exposed to the user and definitions to ease in parsing buttons). Due to this, I\u2019m slightly behind, but anticipate being able to catch up again next week.<\/p>\n
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A video of me running the controller test is available here: https:\/\/www.youtube.com\/watch?v=jU2mdtBN-I0<\/a><\/p>\n <\/p>\n The controller test:<\/p>\n https:\/\/drive.google.com\/file\/d\/1U8mn_7gTbG2sWP3rkUN0vx-6YtHiBfZu\/view?usp=sharing<\/p>\n","protected":false},"excerpt":{"rendered":" This week, my main task was to create the memory mapped I\/O necessary to send controller input from the FPGA to the ARM core. In our design, we chose to use the lightweight AXI bus of the Cyclone V FPGA to accomplish this. Additionally, I set up my FPGA with a linux image that allows … <\/p>\n