This week I worked exclusively on system Verilog coding. I have completed all of the logic needed for basic moves such as bishop, rook, pawn, queen and knight movement.<\/p>\n
I still need to verify the valid move generation works as intended, expect this to be completed towards the beginning of the next week. I will simply feed in a series of board states to the module and verify by hand on a waveform simulation.<\/p>\n
There are a lot of other more subtle moves which I need to complete next week, including castling, castling through check, en passant, etc.<\/p>\n
Looking at the schedule, it seems that the original time allocated to pipelining is being eaten into, but I am pipelining as I go through each different type of move. The hope is that everything is completed at the originally intended time, and I am confident in that happening.<\/p>\n","protected":false},"excerpt":{"rendered":"
This week I worked exclusively on system Verilog coding. I have completed all of the logic needed for basic moves such as bishop, rook, pawn, queen and knight movement. I still need to verify the valid move generation works as intended, expect this to be completed towards the beginning of the next week. I will … <\/p>\n