This week we synthesized onto the DE0-CVs for the first time with our most recent prototype. We immediately encountered a surprise that the board has 18K Adaptive Logic Modules (ALMs) instead of the 49K Logic Elements (LEs) that we were expecting. A quick Google search reveals that these are considered (by Altera) to be equivalent. This is somewhat true. We see 30K\/49K\u00a0 (61%) LEs in Quartus II on the lab machines and 13.7K\/18.5K (74%) ALMs in Quartus 19.1. If we compile with aggressive area optimizations in Quartus 19.1 we get 12..2K\/18.5K (66%) ALMs. We’re still doing ok. While it might be fun to try and squeeze our design onto the DE0-CVs, we do not really see a benefit to doing so, seeing as the DE10-Standard has more resources and we have no real reason to prefer the DE0-CVs. That being said, for now we’ll echo what we said last week and keep a close watch on it. 60-70% usage is reasonable as far as FPGAs go, we should be alright up to ~80% based on what we’ve learned from 18-643.<\/p>\n
We can continue pushing off the FPGA change since the school does have multiple DE-10 Standard boards (or so we’ve been told by other groups) so in the event we need to swap, we can do so without incurring significant cost.<\/p>\n