Looking forward, integration and area consumed are still significant risks to consider. With the full single-player implementation we have 31.3K logic elements used. This is not significantly greater than where we were last week, so presumably the single-player implementation will
Deanyone’s Status Update for February 29
This past week I presented the design review for our team. Overall the presentation went well and everyone else seems to be doing well in their respective projects. The design review report is longer than expected and is taking some
Alton’s Status Update for February 22
This week I primarily focused on getting the sound module working in hardware. Our 8-bit DAC, 3.5mm stereo jack, and jumper wires arrived on Wednesday, so I breadboarded the audio hardware (as designed last week for the middleman board) to
Team Status Update for February 22
This week we synthesized onto the DE0-CVs for the first time with our most recent prototype. We immediately encountered a surprise that the board has 18K Adaptive Logic Modules (ALMs) instead of the 49K Logic Elements (LEs) that we were
Eric’s Status Update for 2/22
Progress Building upon my work from last week, I continued working on the SystemVerilog implementation of the send/receive stack described in last week’s post. I completed the FSMs and handshake sender/receiver this week, leaving the hamming encoder/decoder and top level
Deanyone’s Status Update for February 22
This week I spent the majority of the week getting text to render neatly. This is a necessary feature for us to communicate information to the user. I hard-coded a 6×6 pixel font into a case statement switching between alphanumeric
Alton’s Status Update for February 15
Progress Audio I wrote a SystemVerilog testbench to test loading note data from a file and converting it to a waveform. The note data is stored in a simple hex format: all notes are on an eighth-note grid, and each
Team Status Update for February 15
Risks As mentioned in Deanyone’s status update, we are keeping close watch over the number of logic elements that are being consumed by the design. Our current prototypes are consuming 29K/115K logic elements on the lab boards, and require register
Deanyone’s Status Update for February 15
Prior Work This being the first weekly status update, I’ll include a short summary of work done up until this week: Before this week I had worked on basic graphics implementation, being able to render a playfield with an area
Eric’s Status Update for 2/15
Progress Prior to the proposal presentation we had already made significant strides on the overall system design and game logic implementation. My focus has largely been on the networking aspect of our project – how we interface and communicate between