Progress
Building upon my work from last week, I continued working on the SystemVerilog implementation of the send/receive stack described in last week’s post. I completed the FSMs and handshake sender/receiver this week, leaving the hamming encoder/decoder and top level modules before I can start testing on the boards. Implemented components have been tested in simulation.
Scheduling
I was hoping to have the entire send/receive stack implemented as of writing this post, but other obligations reared their head this week and so I am approximately ~2 days behind where I would like to be. That said, following the original schedule was fairly ambitious considering that the protocol design took longer than planned, and I was banking on completing the entire implementation in one week to stay on schedule. Thankfully I was pretty generous with allocating time for the next tasks, and these early stages of design and implementation are the most crucial so I would rather spend more time here. I should be able to finish up implementation in the next 2-3 days and test everything on the actual boards instead of simulation by the end of next week. From there, further testing will require integration with the game logic, which can be left for the week before spring break.