Progress<\/b><\/p>\n
Eric and I worked together on writing the Python simulation of the tiles (representing a tile\u2019s sides, connections between its neighbors, clocks, etc). Then, after establishing the communication protocol with Eric, I began working on writing the actual firmware logic in Python to test our embedded logic. So far, I have some aspects of the state machine logic for what each tile\u2019s side should do during a falling and rising edge of the clock, and what they should do during certain bits of a word. I also hope to use semi-Test Driven Development with this Python embedded code. I have begun to write unit tests to test small aspects of the code and logic.<\/span><\/p>\n As I\u2019m writing the Python code, I\u2019m beginning to see the value of simulating the tiles and firmware in Python before moving on to the actual Atmega environment. I stumbled upon a few holes and missing parts of our logic, and I\u2019m glad that I\u2019m discovering them now.<\/span><\/p>\n Current progress can be found under \u201ctileFirmware.py\u201d and \u201ctileFirmwareSimulator.py\u201d of our repository: <\/span>https:\/\/github.com\/melodeeli98\/codeblox-capstone<\/span><\/a><\/p>\n Schedule<\/b><\/p>\n The logic isn\u2019t code-complete yet, but I\u2019m still pretty on schedule with this part of the project; I still have a week to complete it.<\/span><\/p>\n Goals for next week:<\/b><\/p>\n Progress Eric and I worked together on writing the Python simulation of the tiles (representing a tile\u2019s sides, connections between its neighbors, clocks, etc). Then, after establishing the communication protocol with Eric, I began working on writing the actual firmware logic in Python to test our embedded logic. So far, I have some aspects of the state machine logic for what each tile\u2019s side should do during a falling and rising edge of the clock, and what they should do…<\/p>\n\n