Progress
This week I finished building the DAC module that sends all of the clocking and data from the FPGA to the DAC and out to audio eventually. We ran into a bit of an issue since we had wanted to work with a 50MHz clock, but the FPGA GPIOs cannot handle that clock speed, we had to lower our clock speed slightly so that the DAC could read it. I also built and tested a few of the filters that I had designed and they work with a roughly 1% error in the 3dB point, as expected.
Scheduling
I’m roughly back on track, as I’ve caught up with where I should be on the schedule. We’ve already begun our testing and integration, so we’re a little bit ahead of schedule there.
