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Gleb’s Status Report for 10/18

Completed simulations of the LED driver circuit and designed the LED PCB assembly.

Simulation

  • Solved PSPICE solver convergence issues by setting initial conditions and tuning other simulation parameters.
    • The problem is very stiff due to a wide bandwidth of frequencies involved (from 250kHz CC driver switching frequency to >100MHz edge harmonics in the LED-MOSFET current loop.  Furthermore, numerous diodes induce non-linearities.
  • Verified in simulation that the chosen snubber circuit can successfully dampen the >100MHz ringing on the rising edge of the modulation clock.
  • Validated simulation results with multiple sets of values for parasitic inductances and capacitances in the circuit.

PCB Layout

The LEDs need to be mounted on an aluminum-core PCB. However, JLC’s process only supports single-layer aluminum-core boards. It is not feasible to lay out the CC drivers on one-layer board, so the illumination module will consist of a two-board assembly: a standard 4-layer FR-4 board with the CC drivers, as well as an aluminum-based board with just the modulation loop. The modulation board has been laid out, while the driver board is in progress. See pictures of both boards below:

 

Modulation board (3D, note eight LEDs in the center):

Modulation board (layout, 4 channels each with two LEDs):

CC Driver board:

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Gleb’s Status Report for 9/27/2025

  • Primarily busy with clock architecture + design presentation
    • We need to supply synchronized clocks to the EPC660 sensor IC and the LED driver. The clocks should be synchronized, with the sensor clock being double the frequency of the modulation clock. Furthermore, the phase delay should be adjustable to enable to allow us to run the sensor in the imaging mode, and to allow us to compensate signal propagation delay between boards.
    • I have explored different discrete clock generation solutions, while Sid has looked into clock generation on STM32 directly. For instance, I have looked into using an external PLL chip or a flipflop frequency divider. Additionally, I have explored adding a quadrature signal and using VGAs to enable the phase shifting.
    • Our final solution  is using Si5338 four-channel clock generation IC. It supports both single-ended and LVDS signalling, which is convenient for using it with EPC660 as well as the modulation driver. The frequency and phase delays will be configured from the MCU via I2C.
  • I have also imported LED and driver models into PSPICE.
  • I will be running simulations and designing the LED PCB next week.
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Gleb Ryabtsev’s Status Report for 9/20

  • Researched various high-power high-frequency LED driver configurations.
  • Settled on EPC21603, a 100MHz laser diode driver.
  • Prepared P-Spice models and environment but haven’t ran comprehensive simulations yet.
  • My progress is on track. We are planning to spend the next week running the P-Spice simulation and doing some more testing on an STM32 breakout board. Once those steps are complete, we can proceed with designing the PCBs.
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Team Status Report for 9/20

  • Our project relies heavily on custom high-speed mixed-signal PCB design. Issues with the PCB performance can jeopardize the success of our project. We are taking steps to de-risk:
    • We are running P-Spice simulations of the analog circuitry to verify the high-frequency behavior (at steady state).
    • We are doing test on an STM32 F7 eval board to make sure that we can generate synchronized modulation clocks for the LED and the sensor chip. See the picture below.
  • We haven’t changed the system design, but we have worked out the specifics of the LED modulator circuit.
  • No schedule updates.