Gleb’s Status Report for 10/18

Completed simulations of the LED driver circuit and designed the LED PCB assembly.

Simulation

  • Solved PSPICE solver convergence issues by setting initial conditions and tuning other simulation parameters.
    • The problem is very stiff due to a wide bandwidth of frequencies involved (from 250kHz CC driver switching frequency to >100MHz edge harmonics in the LED-MOSFET current loop.  Furthermore, numerous diodes induce non-linearities.
  • Verified in simulation that the chosen snubber circuit can successfully dampen the >100MHz ringing on the rising edge of the modulation clock.
  • Validated simulation results with multiple sets of values for parasitic inductances and capacitances in the circuit.

PCB Layout

The LEDs need to be mounted on an aluminum-core PCB. However, JLC’s process only supports single-layer aluminum-core boards. It is not feasible to lay out the CC drivers on one-layer board, so the illumination module will consist of a two-board assembly: a standard 4-layer FR-4 board with the CC drivers, as well as an aluminum-based board with just the modulation loop. The modulation board has been laid out, while the driver board is in progress. See pictures of both boards below:

 

Modulation board (3D, note eight LEDs in the center):

Modulation board (layout, 4 channels each with two LEDs):

CC Driver board:

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