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Sid’s Status Report for 10/18

Updates:

  • Wrote firmware for initialization of EPC660 through I2C commands
  • Helped finish up the design report
  • Schematics + layout in progress of power distribution board: chose buck + bipolar power supplies to provide enough current for analog functionalities of EPC660 and digital high power modulation of LEDs

Next week:

  • Currently on schedule to get the boards ordered by Monday, firmware should be in a place to test by the time they get here in two weeks. Gonna finish laying out the board tomorrow + Monday so that it’s ready for order.

 

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Gleb’s Status Report for 10/18

Completed simulations of the LED driver circuit and designed the LED PCB assembly.

Simulation

  • Solved PSPICE solver convergence issues by setting initial conditions and tuning other simulation parameters.
    • The problem is very stiff due to a wide bandwidth of frequencies involved (from 250kHz CC driver switching frequency to >100MHz edge harmonics in the LED-MOSFET current loop.  Furthermore, numerous diodes induce non-linearities.
  • Verified in simulation that the chosen snubber circuit can successfully dampen the >100MHz ringing on the rising edge of the modulation clock.
  • Validated simulation results with multiple sets of values for parasitic inductances and capacitances in the circuit.

PCB Layout

The LEDs need to be mounted on an aluminum-core PCB. However, JLC’s process only supports single-layer aluminum-core boards. It is not feasible to lay out the CC drivers on one-layer board, so the illumination module will consist of a two-board assembly: a standard 4-layer FR-4 board with the CC drivers, as well as an aluminum-based board with just the modulation loop. The modulation board has been laid out, while the driver board is in progress. See pictures of both boards below:

 

Modulation board (3D, note eight LEDs in the center):

Modulation board (layout, 4 channels each with two LEDs):

CC Driver board:

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Team Status Report for 10/18

What we did this week:

  • Completed layout and part selection of interface PCB, designing for high speed signals
  • Completed the simulation, design, and layout of the two illumination PCBs.

Part A(Claire):  Our ToF imaging system addresses a global need for accessible, reliable, and cost effective 3D sensing in aquatic environments. Existing technologies like sonar and lidar are often expensive, bulky, and energy-intensive, limiting their use to large institutions or well-funded operations. By leveraging visible light illumination, custom PCB design, and commercially available components, our end goal product offers a compact and affordable solution suitable for research, environmental monitoring, and underwater robotics worldwide. This enables broader implementations in underwater exploration and supports global efforts in marine conservation, environmental data collection, and structural and technological accessibility beyond academic or high resource settings.

 

Part B: Not applicable. Our ToF sensor is a component of a larger system (AUV). As such, it does not address any cultural need.

 

Part C (Gleb): In general, the ToF sensor doesn’t address a specific environmental need, but the robotic system on which it is mounted might. With that, the ToF can conceivably impact some marine organisms in its immediate vicinity due to light emission. However, we are also hopeful that the ToF will replace sonars in some applications. Sonars are known to have a significant impact on marine life at large distances.

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Claire’s Status Report for 10/18

Completed interface PCB layout passing general design rules.

Things I kept in mind to mitigate EMI and clean high frequency signals:

  • Routing on single layer with no vias, keeping traces straight and short as possible for priority high frequency signals (clock signals)
  • Careful part selection with low esr (equivalent series resistance) capacitors and generally compact 0603 to 0402 packages
  • Decoupling capacitors located immediately next to corresponding pins on the same layer, each with its own 3V3 power via
  • xtal crystal oscillators immediately next to pins on the same layer
  • Continuous solid ground plane on layer 2
  • Matching trace lengths and series resistors
  • Bulk tantalum capacitors on input power supplies
  • Ferrite beads for clean analog power pins

On schedule, will finalize design with team and order boards + components.

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Sid’s Status Report for 10/4

This week, I worked on getting the firmware to build. I registered all of the interrupts for the GPDMA controller and the DCMI interface. I had to fix a lot of errors related to the weak function callbacks, etc. I now just have to write the main loop and set up the half-full buffer interrupt to transfer the data to Ethernet. I also contacted vendors about our breakout board to make sure that we were getting the correct one and placed a couple orders.

Next week, I plan to test my code on a Nucleo if it arrives in time. I am on schedule, as there are only a few more functions in firmware to develop before it is ready to flash.

 

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Team Status Report for 10/4

Working through calculations and details of design report.

Additional circuitry and component selection for interface PCB, finalizing LED driver PCB with supporting simulations.

Collecting parts to order, specifically those needed to verify firmware and conduct preliminary tests that don’t require the custom PCBs.

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Sid’s Status Report for 9/27

This week, I worked on generating peripheral clock configurations and verified that the MCU we chose would work with all of the peripherals we needed. I also determined how to set up the GPDMA peripheral to properly route data. In addition, I worked on the design presentation and made some block diagrams for our HW/SW architecture.

I am on schedule for now, I need to get DMA and UDP code done over the next week and make sure it is compiling, so that is my main goal.

 

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Team Status Report for 9/27

Selected specific STM32 chip (STM32H563RI) and configured peripherals.

Selected clock modulation IC that works with EPC660 and EPC21603 (single ended + LVDS differential, respectively).

PCBs of MCU+interface and control board schematics underway, along with verifying design through simulations.

Design presentation preparations and communication of necessary requirements across modules and firmware.

No pushbacks in schedule nor changes in design.

 

 

Part A(Sid):

The Illuminator can be beneficial for many aspects of public safety and welfare. Underwater robots are required in many critical applications such as water tower maintenance and underwater shipwreck recovery operations. By increasing the resolution, cost-effectiveness, and field of view of these robots using a visible light ToF camera, loss of life can be prevented by increasing the effectiveness of recovery operations. In addition, water towers can suffer from corrosion and leakage of poisonous materials. By accurately inspecting scale and buildup on the inside of water towers with robots, these dangerous growths can be identified earlier before they leach into supplies.

PartB(Claire): Not applicable. Our sensor system does not ignite social activities in any way as it does not have a human to human interaction in its design. It does not emphasize cultural awareness or political campaigns, and is not intended for any of those purposes.

PartC(Gleb): The main application of our underwater ToF camera is to provide volumetric vision capability to AUVs doing close-range manipulation. In general, AUVs are expensive, with prices in tens or hundreds of thousands dollars. Therefore our sub-$1000 sensor will constitute only a small fraction of the vehicle cost.

Currently, the only feasible alternative for close-range 3D vision underwater are stereo-cameras. A high-quality stereo-pair cost is typically $500 or more. For example, the cameras used for stereo-vision on TartanAUV’s Osprey submarine cost around $3500 each. Therefore, our system is very competitive in terms of cost. Additionally, a ToF sensor has certain advantages over stereo-pairs, which we discussed in our design proposal.