What did you personally accomplish this week on the project?
This week I finalized the testing and bring-up plan with detailed procedures for USB signal integrity verification and power cycling characterization. The plan now includes specific test sequences for each verification stage: initial continuity checks of critical nets, FTDI enumeration testing at low power, signal integrity measurements of USB differential pairs using the vector network analyzer, and full VBUS power cycling with actual failed drives. I documented the expected voltage levels, rise times, and impedance measurements at each test point to establish clear pass/fail criteria.
I received and inventoried the standard lead-time components that arrived this week, including the bulk capacitors, resistors. I verified all quantities and part numbers against our BOM – everything matched perfectly and we have sufficient quantities for the initial prototype builds plus spares. One connector I had to do a replacement oder from.
I completed the hardware interface specification document detailing GPIO pin assignments for VBUS power control, timing requirements for power cycling sequences (minimum 500ms off-time between cycles, 100ms ramp monitoring), and USB enumeration signal monitoring points. This document provides Apollo with all the information needed for PyFTDI integration.
However, we encountered a significant issue this week: the TUSB1064 USB redriver IC that I had ordered went out of stock at our supplier before the order could be fulfilled. This component is critical for signal conditioning and was a key part of our design for handling degraded USB signals from failed drives. After investigating alternatives and consulting with Apollo, we made the decision to redesign the board to use a different, more readily available redriver IC. I completed the schematic updates, re-routed the affected PCB traces while maintaining our impedance-controlled design requirements, and placed a new fabrication order. The new timeline puts us at approximately 2 weeks for fabrication and assembly, pushing our expected delivery to around November 14th.
I met with Apollo to review the software prototype integration. We successfully demonstrated a working software prototype that can communicate with the FTDI chip and control GPIO pins for power sequencing. This de-risks a major portion of the project since we’ve now validated that the PyFTDI library works as expected for our use case and can handle the timing-critical power cycling operations.
Is your progress on schedule or behind? If you are behind, what actions will be taken to catch up to the project schedule?
I am approximately one week behind schedule due to the component availability issue and required board redesign. The new expected delivery date of November 14th represents a one-week slip from our original November 7th target.
To mitigate this delay, I’ve taken several actions: First, I expedited the new PCB fabrication order by selecting the faster turnaround option (7-day instead of 10-day fabrication). Second, Now ive started to also work on the software. Apollo can continue developing and testing the recovery algorithms without waiting for hardware, effectively parallelizing our work streams. Third, I’m pre-positioning all other components and test equipment so that we can begin board bring-up immediately upon delivery rather than waiting for additional setup time. Finally, I’ve identified which test procedures can be streamlined during initial bring-up without compromising safety or thoroughness, potentially recovering 1-2 days during the validation phase.
What deliverables do you hope to complete in the next week?
Next week I plan to:
- Receive and inventory the long-lead-time components (IRLZ44N MOSFETs and the replacement USB redriver IC) and verify they match specifications
- Develop a comprehensive risk mitigation strategy document for the board bring-up phase, including contingency plans for out-of-spec impedance measurements, VBUS timing issues, and signal integrity problems
- Prepare detailed assembly instructions for the replacement USB redriver component, including any layout differences from the original design
- Check if the labs have the test equipment do test our signal integrity results.
- Work with Apollo to expand the software prototype to include data recovery test cases that we can validate immediately when hardware arrives
- Create a revised project schedule that accounts for the one-week slip and identifies opportunities to recover time in later phases