1. Most significant risks and management strategies
The primary risks have shifted toward integration and timing verification as the project moves from design to early implementation. On the hardware side, PCB fabrication is now underway. The major risk is ensuring the MOSFET-based VBUS power-cycling circuit meets the < 10 ms rise/fall and ≤ 5 % overshoot specification once boards arrive. To mitigate this, Mars has scheduled oscilloscope validation immediately after bring-up and has kept a secondary vendor on standby in case of fabrication defects.
For software, the key challenge is synchronizing FTDI GPIO control with sustained data capture without exceeding the 20 µs jitter budget. We are addressing this by building a modular Python test suite that logs timing metrics separately from recovery logic, allowing us to debug latency before full system integration.
File-system reverse-engineering remains a longer-term risk, but work continues on a simplified recovery path that performs raw sector imaging first, followed by optional error-correction passes.
2. Changes to system design
No architectural changes were introduced this week. Minor schematic tweaks were made before sending the board out for fabrication — primarily tightening trace routing on the differential USB pairs and relocating decoupling capacitors for better impedance control.
Software structure remains the same (control / capture / reconstruction), but module boundaries have been clarified in the documentation to improve parallel development between hardware and software.
3. Schedule update
We remain on schedule with the Gantt chart milestones:
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Week 5–6 (current): PCB fabrication + software modularization and sustained logging tests.
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Week 7–8: Board assembly and FTDI GPIO verification.
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Week 9–10: System integration and initial data recovery trials.
Fabrication lead-time estimates confirm that boards will arrive in roughly two weeks, aligning with our planned integration window.
4. Progress summary
This week’s focus was on transitioning from design to execution.
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Hardware: Finalized and submitted PCB Gerber files for fabrication; reviewed component order confirmations and arranged assembly logistics.
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Software: Expanded the FTDI framework beyond initial tests to support continuous byte logging and modular control. Initial throughput measurements will begin once sample data is available.
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Documentation: Updated design documentation to reflect final board stack-up, test metrics, and risk mitigation strategies.
Overall, the project has successfully moved from planning into early implementation, with both tracks maintaining momentum.