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==== Verilog Tutorials ==== | ==== Verilog Tutorials ==== | ||
- | While this class will focus on System Verilog, these manuals are useful for additional studies: | + | While this class will focus on System Verilog, these Verilog manuals are useful for additional studies: |
* {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | * {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | ||
* {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | * {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | ||
* {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | * {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | ||
* [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] | * [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] |