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==== ARM ==== | ==== ARM ==== | ||
Throughout this course, we will use the ARM Architecture Reference Manual as the definitive specification for the ARM ISA. All other ARM-related material provided below are only for your benefit. | Throughout this course, we will use the ARM Architecture Reference Manual as the definitive specification for the ARM ISA. All other ARM-related material provided below are only for your benefit. | ||
- | * {{arm_full_reference.pdf|ARM Architecture Reference Manual}} | + | * ARM Architecture Reference Manual |
- | * {{arm-instructionset.pdf|ARM Instruction Set (pdf)}} | + | * [[https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf|Manual (5MB)]] |
+ | * ARM Architecture Instruction Quick Reference | ||
+ | * {{arm-instructionset.pdf|Quick Ref (.5MB)}} | ||
+ | * ARM university teaching material: {{http://www.arm.com/support/university/educators/architecture/index.php| Link}} | ||
+ | * There are interesting and potentially useful slides on the ARM ISA: | ||
+ | * {{http://www.arm.com/files/ppt/ARM_Teaching_Material.ppt| ARM Teaching material}} | ||
+ | * {{http://www.arm.com/files/ppt/ARM_Processors_and_Architectures_-_Uni_Program_.pptx| ARM Univ. Program}} | ||
+ | * {{http://www.arm.com/files/pdf/ARM_Arch_A8.pdf| A8 Architecture}} | ||
==== MIPS ==== | ==== MIPS ==== | ||
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* (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | * (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | ||
- | ==== ARM ==== | ||
- | * ARM Architecture Reference Manual | ||
- | * [[https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf|Manual (5MB)]] | ||
- | * ARM Architecture Instruction Quick Reference | ||
- | * {{arm-instructionset.pdf|Quick Ref (.5MB)}} | ||
==== Alpha ==== | ==== Alpha ==== | ||
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Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | ||
- | ===== Verilog Tutorials ===== | + | ==== System Verilog Tutorials ==== |
- | While this class will focus on System Verilog, these manuals are useful for additional studies: | + | * {{http://www.asic-world.com/systemverilog/tutorial.html|ASIC World System Verilog Tutorial}} |
+ | * {{http://www.eda.org/sv/SystemVerilog_3.1a.pdf|SystemVerilog 3.1a Language Reference Manual}} | ||
+ | |||
+ | ==== Verilog Tutorials ==== | ||
+ | While this class will focus on System Verilog, these Verilog manuals are useful for additional studies: | ||
* {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | * {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | ||
* {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | * {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | ||
* {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | * {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | ||
* [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] | * [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] |